Freescale Semiconductor MPC5200B - Manual (Page 410)

Host Control (HC) Operational Registers
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 12-7
Bits Name Description
0:20 — Reserved
21 RWE RemoteWakeUpEnable—HCD uses bit to enable or disable the remote WakeUp feature on
detection of upstream resume signaling.
When this bit is set and the ResumeDetected bit in HcInterruptStatus is set, a remote
WakeUp is signaled to the host system. Setting this bit has no impact on the generation of
hardware interrupt.
22 RWC RemoteWakeUpConnected—bit indicates whether HC supports remote WakeUp signaling.
If remote WakeUp is supported and used by the system it is the responsibility of system
firmware to set this bit during BOOT UP.
HC clears bit on a hardware reset, but does not alter it on a software reset. Host system
remote WakeUp signaling is host-bus-specific and not described in this specification.
23 IR InterruptRouting—bit determines routing of interrupts generated by events registered in
HcInterruptStatus.
The IR Bit is ignored by the MPC5200B. It is here to maintain OHCI compliancy. The interrupt
from the USB module is routed to the interrupt controller in the SIU where it can be routed
to the SMI or NORMAL interrupt.
24:25 HCFS HostControllerFunctionalState—a USB field:
00=USBRESET
01=USBRESUME
10=USBOPERATIONAL
11=USBSUSPEND
Transition to USBOPERATIONAL from another state causes SOF generation to begin 1ms
later.
HCD may determine if HC has begun sending SOFs by reading the StartofFrame field of
HcInterruptStatus. This field may be changed by HC, only when in the USBSUSPEND state.
HC may move from the USBSUSPEND state to the USBRESUME state after detecting
resume signaling from a downstream port. HC enters USBSUSPEND after a software reset,
whereas it enters USBRESET after a hardware reset. A hardware reset also resets the Root
Hub and asserts subsequent reset signaling to downstream ports.
26 BLE BulkListEnable—setting bit enables Bulk list processing in next Frame.
• If cleared by HCD, Bulk list processing does not occur after next SOF. HC checks this bit
whenever it determines to process the list. When disabled, HCD may modify the list.
• If HcBulkCurrentED points to an ED to be removed, HCD advances pointer by updating
HcBulkCurrentED before re-enabling list processing.
27 CLE ControlListEnable—setting bit enables Control list processing in next Frame.
• If cleared by HCD, Control list processing does not occur after next SOF. HC checks this
bit whenever it determines to process the list. When disabled, HCD may modify the list.
• If HcControlCurrentED points to an ED to be removed, HCD advances pointer by
updating HcControlCurrentED before re-enabling list processing.
28 IE IsochronousEnable—HCD uses bit to enable/disable isochronous EDs processing. While
processing the periodic list in a Frame, HC checks bit status when it finds an Isochronous
ED (F=1).
• If set (enabled), HC continues processing the EDs.
• If cleared (disabled), HC halts periodic list processing, which now contains only
isochronous EDs, and begins processing Bulk/Control lists.
Setting this bit is guaranteed to take effect in the next Frame, not the current Frame.