Freescale Semiconductor MPC5200B - Manual (Page 421)

MPC5200B Users Guide, Rev. 1
12-18 Freescale Semiconductor
Host Control (HC) Operational Registers
12.4.4.4 USB HC Periodic Start Register—MBAR + 0x1040
This register has a 14-bit programmable value that determines when is the earliest time HC should start processing the periodic list.
12.4.4.5 USB HC LS Threshold Register—MBAR + 0x1044
This register contains an 11-bit value used by the HC to determine whether to commit to the transfer of a maximum 8-Byte LS packet before
EOF. Neither the HC nor HCD are allowed to change this value.
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb
R FN
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
16:31 FN FrameNumber—is incremented when HcFmRemaining is re-loaded. FN rolls over to 0 after
ffff.
When entering the USBOPERATIONAL state, this is automatically incremented. Content is
written to HCCA after HC has incremented the FN at each frame boundary and sent a SOF,
but before HC reads the first ED in that frame. After writing to HCCA, HC sets the
HcInterruptStatus StartofFrame.
0:15 — Reserved
Table 12-17. USB HC Periodic Start Register
msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R Reserved
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lsb
R Reserved PS
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
0:17 — Reserved
18:31 PS PeriodicStart—field is cleared after a hardware reset. PS is then set by HCD during HC
initialization. PS value is calculated roughly as 10% off from HcFmInterval. A typical value is
3E67.
When HcFmRemaining reaches the value specified, processing of periodic lists has priority
over Control/Bulk processing. HC then starts processing the Interrupt list after completing the
current Control or Bulk transaction in progress.
Table 12-18. USB HC LS Threshold Register
msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R Reserved
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0