Freescale Semiconductor MPC5200B - Manual (Page 608)

SPI Registers—MBAR + 0x0F00
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 17-7
17.3.5 SPI Data Register—MBAR + 0x0F09
17.3.6 SPI Port Data Register—MBAR + 0x0F0D
17.3.7 SPI Data Direction Register—MBAR + 0x0F10
Table 17-9. SPI Data Register
msb 0 1 2 3 4 5 6 7 lsb
R D7 D6 D5 D4 D3 D2 D1 D0
W
RESET: 0 0 0 0 0 0 0 0
Bit Name Description
0:7 D[0:7] The SPI Data register is both an input and output register for SPI data.
Attempts to write to this register while data transfers are in progress sets the WCOL flag and
disables the attempted write. Review the WCOL bit description in
Table 17-8 for more
information.
Reading data can occur anytime, from after SPIF is set, to before the end of the next transfer. If
SPIF is not serviced by the end of the successive transfers, those data bytes are lost and data
within SPIDR retains the first byte until SPIF is serviced.
Table 17-10. SPI Port Data Register
msb 0 1 2 3 4 5 6 7 lsb
R D7 D6 D5 D4 D3 D2 D1 D0
W
RESET: 0 0 0 0 0 0 0 0
Bit Name Description
0:7
(Note 1)
D[0:7] SPI Port Data bits—data written to SPIPORT drives pins only when they are configured as
general-purpose outputs.
Reading an input (data direction bit is clear) returns the pin level.
Reading an output (data direction bit is set) returns the pin driver input level.
Writes do not change the state of pins 0:3 when pin is configured for SPI output.
SPIPORT I/O function depends upon the state of the SPE bit in SPI control register 1 and
the state of each associated data direction bit in SPIDDR.
Note:
1. Bits 4:7 do not drive output pins. When programmed as inputs (data direction bit is set), they return "0".
Table 17-11. SPI Data Direction Register
msb 0 1 2 3 4 5 6 7 lsb
R DDR7 DDR6 DDR5 DDR4 DDR3 DDR2 DDR1 DDR0
W
RESET: 0 0 0 0 0 0 0 0
Pin
Function
SS SCK MOSI MISO