Freescale Semiconductor MPC5200B - Manual (Page 42)

Architecture
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 1-7
MSCAN supports both standard and extended identifier (ID) message formats specified in BOSCH CAN protocol specification, revision 2.0,
part B. Each MSCAN module contains:
• 4 receive buffers (with FIFO storage scheme)
• 3 transmit buffers
• flexible maskable identifier filters
1.2.4 Byte Data Link Controller - Digital BDLC-D
The MPC5200B supports J1850 Class B data communication network interface compatible and ISO compatible for low speed (<125kbps)
serial data communications in automotive applications.
• Hardware cyclical redundancy check (CRC) generation and checking
• Two power saving modes with automatic wake up on network activity
• Polling and CPU interrupt available
• Block mode receive/transmit supported
• Supports 4X mode, 41.6 kbps
• In-frame response (IFR) types 0, 1, 2, and 3 supported
• Wake up on J1850 message
1.2.5 System Level Interfaces
System Level Interfaces are listed below and described in the sections that follow:
• Chip Selects
• Interrupt Controller
• Timers
• General Purpose Input/Outputs (GPIO)
• Functional Pin Multiplexing
• Real-Time Clock (RTC)
1.2.5.1 Chip Selects
The MPC5200B integrates the most common system integration interfaces and signals. There are 8 fully programmable external chip selects,
which are independent of the SDRAM interface. LP_CS0 has special features to support a Boot ROM. Two of the chip selects may be used
by the IDE disk drive interface, when enabled.
1.2.5.2 Interrupt Controller
The Interrupt Controller has 4 external interrupt signals and manages both external and internal interrupts. All interrupt levels and priorities
are programmable.
The Interrupt Controller takes advantage of the new critical interrupt feature defined by the PowerPC architecture. This allows e300 core
interrupts outside operating system boundaries, for critical functions such as real-time packet processing.
1.2.5.3 Timers
MPC5200B integrates several timer functions required by most embedded systems:
• Two internal Slice timers can create short-cycle periodic interrupts.
• A WatchDog timer can interrupt the processor if not regularly serviced, catching software hang-ups.
A bus monitor monitors bus cycles and provides an interrupt if transactions take longer than a prescribed time.
1.2.5.4 General Purpose Input/Outputs (GPIO)
A total of 56 pins on the MPC5200B can be programmed as GPIOs.
• 8 pins can interrupt the processor.
• 8 pins can support a “Wake Up” capability that brings the MPC5200B out of low power modes.
• 8 pins are “output only” GPIOs.
The remaining GPIO pins support a simple “set the output level” or “detect the input level” type GPIO function. Eight I/Os can be connected
to one of eight general purpose timers to support input capture, output compare or pulse width modulation functions.
The number of GPIOs available in the various modes depends on the peripheral functionality required. See pin descriptions and I/O port maps
below for more information.