Freescale Semiconductor MPC5200B - Manual (Page 190)

General Purpose I/O (GPIO)
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 7-31
7.3.2.1.2 GPS Simple GPIO Enables Register — MBAR + 0x0B04
20:23 PSC3 Programmable Serial Controller 3
0000 = All PSC3 pins are GPIOs
0001 = USB2 on PSC3, no GPIOs available, see Note 3
001X = Reserved
0100 = UART functionality without CD
0101 = UARTe functionality with CD
0110 = CODEC3 functionality
0111 = CODEC3 functionality (with MCLK)
100X = SPI
101X = Reserved
1100 = SPI with UART3
1101 = SPI with UART3e
111X = SPI with CODEC3
24 — Reserved
25:27 PSC2 Programmable Serial Controller 2
000 = All PSC2 pins are GPIOs
001 = CAN1&2 on PSC2 pins, see Note 3
01X = AC97 functionality
100 = UART functionality without CD
101 = UARTe functionality with CD
110 = CODEC2 functionality(without MCLK)
111 = CODEC2 functionality (with MCLK)
28 — Reserved
29:31 PSC1 Programmable Serial Controller 1
00X = All PSC1 pins are GPIOs
01X = AC97 functionality
100 = UART functionality without CD
101 = UARTe functionality with CD
110 = CODEC1 functionality (without MCLK)
111 = CODEC1 functionality (with MCLK)
Note:
1. ALT CAN cannot exist with ATA on Tmr0/1, not with CAN on PSC2.
2. ALT SPI cannot exist with any SPI on PCS3.
3. USB cannot exist on both Either and PSC3.
4. See Section 7.3.1, GPIO Pin Multiplexing or Table 2-1 or Table 2-2 to determine GPIO availability for the various
PCR field settings.
5. If Large Flash or Most Graphics mode is enabled at boot, using a reset configuration bit, PCI disable will come out of
reset set to 1. If these modes are not enabled at boot, this bit will come out of reset set to 0.
6. PSC3_4 and PSC3_5 default to zero (interrupt gpio) after reset. However, if the PSC3 is pro-grammed to USB2 mode
RXP and RXN will be on these pins. If PSC is programmed to UARTe mode, CD will be on the PSC3_4 pin.
Table 7-22. GPS Simple GPIO Enables Register
msb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Name Description