Freescale Semiconductor MPC5200B - Manual (Page 681)

MPC5200B Users Guide, Rev. 1
20-2 Freescale Semiconductor
Modes of Operation
Figure 20-1. BDLC Operating Modes State Diagram
• Power Off
This mode is entered from the Reset mode whenever the BDLC module supply voltage V
dd
drops below its minimum specified
value for the BDLC module to guarantee operation. The BDLC module will be placed in the Reset mode by a system Low Voltage
Reset (LVR) before being powered down. In this mode, the pin input and output specifications are not guaranteed.
• Reset
This mode is entered from the Power Off mode whenever the BDLC module supply voltage V
dd
rises above its minimum specified
value (V
dd(MIN)
) and some MCU reset source is asserted. To prevent the BDLC from entering an unknown state, the internal MCU
reset is asserted while powering up the BDLC module. BDLC Reset mode is also entered from any other mode as soon as one of
the MCU’s possible reset sources (e.g. LVR, POR, COP watchdog, Reset pin etc.) is asserted.
In this mode, the internal BDLC module voltage references are operative, V
dd
is supplied to the internal circuits, which are held in
their reset state and the internal BDLC module system clock is running. Registers will assume their reset condition. Outputs are held
in their programmed Reset state, inputs and network activity are ignored.
• BDLC Disabled
This mode is entered from the Reset mode after all MCU reset sources are no longer asserted. It is entered from the Run mode
whenever the BDLCE bit in the BDLC Control Register is cleared.
In this mode the mux interface clock (f
bdlc
) is stopped to conserve power and allow the BDLC module to be configured for proper
operation on the J1850 bus. The IP bus interface clocks are left running in this mode to allow access to all BDLC module registers
for initialization.
V
dd
> V
dd
(Min.) and
Power Off
Reset
BDLC Stop
Run
V
dd
≤ V
dd
(Min.)
STOP instruction or
(from any mode)
BDLC Wait
Network activity or
(WAIT instruction and WCM=1)
(WAIT instruction and WCM=0)
Any MCU reset source asserted
No MCU reset source asserted
Any MCU reset source asserted
Network activity or
other MCU wake-up
other MCU wake-up
BDLCE set in DLCSCR
BDLC
BDLCE cleared in DLCSCR
Disabled