Freescale Semiconductor MPC5200B - Manual (Page 559)

MPC5200B Users Guide, Rev. 1
15-48 Freescale Semiconductor
PSC Operation Modes
Figure 15-5. Timing Diagram—Receiver
When the receiver detects a high-to-low (mark-to-space) transition of the start bit on RxD, the state of RxD is sampled. It samples each 16 ×
clock for eight clocks, starting one-half clock after the transition (asynchronous operation) or at the next rising edge of the bit-time clock
(synchronous operation).
• If RxD is sampled high, start bit is invalid; a valid start bit search begins again.
• If RxD is still low, a valid start bit is assumed and receiver continues sampling input at 1-bit time intervals at the theoretical center
of the bit. This continues until the proper number of data bits and parity, if any, is assembled and 1 stop bit is detected.
RxD input data is sampled on the rising edge of the programmed clock source. The lsb is received first. Data is then transferred to a receiver
holding register and
SR [RxRDY] is set. If the character is less than 8bits, the most significant unused bits in the receiver holding register are
cleared.
If the MR2 [TxRTS] bit was set to one then the user must control the RTS line by writing to the output port register. For all user generated
commands to the UART receiver, like enable RX, disable RX or set break, the user must set the associated RTS signal by writing the OP0 or
OP1 register. But the UART receiver automatically deasserts the RTS signal if the number of received data words reached the FIFO alarm
level and deasserts the RTS line if the number of words in the FIFO falls under the granularity level.
After the stop bit is detected, the receiver immediately looks for the next start bit.
• If a non-zero character is received without a stop bit (framing error) and RxD remains low for one-half of bit period after stop bit
is sampled, the receiver operates as if a new start bit were detected. Parity error (PE), framing error (FE), overrun error (ORERR),
and received break (RB) conditions set respective error and break flags in
SR at the received character boundary and are valid only
if SR [RxRDY] is set.
• If a break condition is detected (RxD is low for the entire character including the stop bit), a character of all 0s is loaded into the
Receiver Shift Register and
SR [RB,RxRDY] are set. RxD must return to a high condition for at least one-half bit-time before a
search for the next start bit begins.
The receiver will detect the beginning of a break in the middle of a character, if the break persists through the next character time.
• If the break begins in the middle of a character, the receiver places the damaged character in the Rx FIFO stack and sets the
corresponding
SR error bits and SR [RxRDY].
• If the break lasts until the next character time, the receiver places an all-0 character into the Rx FIFO and sets SR [RB,RxRDY].
15.3.1.5 Configuration Sequence for UART Mode
Table 15-76 shows the configuration sequences. This list includes the UART mode related registers only, not the other configure values like
interrupt and FIFO configurations. PSC module registers can be accessed by word or byte operations.
C1 C2 C4 C6 C7 C8 C3 C5
C6, C7, and C8 are lost
(C2)
Status
Data
(C3)
Status
Data
(C4)
Status
Data
C5 is
lost
Reset by
command
TxD
Receiver
Enabled
SR [RxRDY]
Overrun
RTS
Internal
Module
Select
SR [FFULL]
(C1)
Status
Data
S R [ORERR ]
Automatically asserted
when ready to receive
Manually asserted first time,
automatically negated if overrun occurs
OP0[RTS] = 1
Automatically deasserted
when FIFO reached the
alarm level