Freescale Semiconductor MPC5200B User Manual
Page 625
MPC5200B Users Guide, Rev. 1
18-8
Freescale Semiconductor
I
2
C Interface Registers
1.
Identify all rows of Table 18-4 where SCL Period satisfies criteria (5). This set of rows limits the choices of SCL allowed for this
particular system clock.
2.
Calculate the SCL associated with these rows according to (1), and decide which speeds are “acceptable” (fast enough or slow
enough) for the system.
3.
Then, find the subset of those rows associated with the “acceptable” I2C clock speeds such that SDA Hold satisfies criteria (6).
4.
Choose the preferred FDR setting from among that subset that meets (5) and (6).
5.
Check that the preferred FDR setting also satisfies (7) and (8) - usually it does. If not, then choose a different FDR setting that
meets (5), (6), (7), and (8).
Likewise, for fast mode I2C, the I2C specification states that
(SCL <= 400 kHz)
AND
(0.3 us <= SDA Hold Time <= 0.9 us)
AND
(SCL Hold of START >= 0.6 us)
AND
(SCL Hold of STOP >= 0.6 us)
which means that the system programmer must choose SCL Period, SDA Hold, SCL Hold of START, and SCL Hold of STOP from Table
18-4 to satisfy the following four equations (9) through (12):
SCL Period >= (1/400,000) * [system clock speed (in Hz) (9)
AND
(0.0003)*[SCL (in kHz)]*(SCL Period) <= SDA Hold <= (0.0009)*[SCL (in kHz)]*(SCL Period) (10)
AND
SCL Hold of START >= (0.0006)*[SCL (in kHz)]*(SCL Period) (11)
AND
SCL Hold of STOP >= (0.0006)*[SCL (in kHz)]*(SCL Period) (12)
In this case, the simplest strategy for the system programmer to follow is this:
1.
Identify all rows of Table 18-4 where SCL Period satisfies criteria (9). This set of rows limits the the choices of SCL allowed.
2.
Calculate the SCL associated with these rows according to (1), and decide which speeds are “acceptable” (fast enough or slow
enough) for the system.
3.
Then, find the subset of those rows associated with the “acceptable” I2C clock speeds such that SDA Hold satisfies criteria (10).
4.
Choose the preferred FDR setting from among that subset that meets (9) and (10).
5.
Check that the preferred FDR setting also satisfies (11) and (12) - usually it does. If not, then choose a different FDR setting that
meets (9), (10), (11), and (12).
As a final note, the programmer should be aware of the order of the FDR bits in Table 18-4. Additionally there may be several different
combinations of FDR bits that satisfy the system programmer, because Table 18-4 has duplicated entries.
Table 18-4. I2C Frequency Divider Bit Selection
FDR[7,6]
FDR[5,1,0]
FDR[4,3,2]
SCL Period
SDA Hold
SCL Hold
of START
SCL Hold
of STOP
00
000
000
28
9
10
15
00
000
001
44
11
18
23
00
000
010
80
17
34
41