Freescale Semiconductor MPC5200B - Manual (Page 122)

MPC5200B Memory Map
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 3-3
3.3 MPC5200B Memory Map
The MPC5200B memory map has the following main regions:
• MPC5200B Internal Register Space
• External Busses
— SDRAM Bus
— LocalPlus Bus
– External Chip Selects 0 - 7
– Memory Space
– Boot Space
– Program Space
– Data Space
• ATA Space
3.3.1 MPC5200B Internal Register Space
The internal registers of the MPC5200B are memory mapped, just like external RAM or any other peripheral devices. The addresses of the
internal registers are expressed as offsets to the contents of the MBAR Register (Memory Base Address Register).
The Memory Base Address Register contains the upper 16 bits of the register address space. This sixteen bit value is contained in the lower
16 bits (bit 16 - bit 31) of the Memory Base Address Register. The default value at the release of RESET contained in the MBAR Register is
0x0000 8000. To form a register address, the lower sixteen bits of MBAR are left-justified, forming address bits A31 - A16. Then the 16-bit
register offset address for a particular register is concatenated with this value to form a 32-bit address.
NOTE
On the LocalPlus Bus, A31 is the Most Significant Bit and A0 is the Least Significant Bit. It is most
important to note that the internal registers of the MPC5200B use bit 0 as the Most Significant Bit
and bit 31 as the Least Significant Bit.
The Memory Base Address Register is memory mapped, itself, and it is also the first register in the
Internal Register Space. Because the default value in MBAR from the release of RESET is 0x0000
8000 and the MBAR register has an offset address of 0x0000 0000, the absolute address of MBAR
becomes 0x8000 0000.
For an additional example, the offset addresses of the Clock Distribution Module Registers start at 0x0200. Using the default value in MBAR,
the address of the first register in the Clock Distribution Module is 0x8000 0200.
NOTE
The MBAR register is a memory mapped register. In fact, the contents of the MBAR register hold the
Most Significant 16 bits of its own address. When the contents of the MBAR register are changed, a
copy of this value should be written to Special Purpose Register SPR (0d311). This location should
be used to store the present Memory Base Address for the System Memory map. It is the
responsibility of the system programmer to ensure the present value is current with the system’s
memory base offset.
3.3.2 External Busses
There are two external data / address bus structures on the MPC5200B. These are the LocalPlus Bus and the SDRAM Bus. The MPC5200B
always begins execution from the release of RESET on the LocalPlus Bus and from the memory device connected to LP_CS0.
3.3.2.1 SDRAM Bus
The SDRAM BUS is designed to accommodate Synchronous Single Data Rate DRAM and Synchronous Double Data Rate DRAM. Program
execution generally occurs from programs stored in the memory located on the SDRAM Bus. The SDRAM bus has burst read capability which
greatly enhances the bandwidth of the SDRAM Bus. The Memory Clock that drives the SDRAM bus is equal to the XL Bus clock frequency.
From Power On Reset the SDRAM Bus is inactive, that is, the chip select line for the SDRAMs is inactive. The appropriate registers must
first be programmed to configure the SDRAM Bus chip select line and make it active before program execution can begin on the SDRAM
bus. In general, when a system begins operation from a Power On Reset, “programs stored as data” in memory devices on the LocalPlus Bus
are transferred to the SDRAM bus memory by a program stored in the Boot Device on the LocalPlus Bus. Once the “programs stored as data”
are transferred to the SDRAM bus memory, the Boot program then causes the CPU to jump to the start address of the program which is now
located in SDRAM Bus memory and execution continues from the SDRAM Bus memory.