Freescale Semiconductor MPC5200B - Manual (Page 723)

MPC5200B Users Guide, Rev. 1
20-44 Freescale Semiconductor
Functional Description
NOTE
As with a message transmission, the IMSG bit should never be used to ignore the BDLC module’s
own IFR transmissions. This is again due to the BDLC State Vector Register bits being inhibited from
updating until IMSG is cleared, preventing the CPU from detecting any IFR-related state changes
which may be of interest.
20.8.7.1 Receiving an IFR with the BDLC module
Receiving an IFR from the SAE J1850 bus requires the same procedure that receiving a message does, except that as each byte is received the
Received IFR Byte (RxIFR) state is indicated in the BDLC State Vector Register. All other actions are the same. For an illustration of the steps
described below, refer to
Figure 20-18 .
• Step 1: When RxIFR Interrupt Occurs, Retrieve IFR Byte
When the first byte of an IFR following a valid EOD symbol is received that byte is placed in the BDLC Data Register, and an
RxIFR state is reflected in the BDLC State Vector Register. No indication of the EOD reception in made, since the RxIFR state will
indicate that the main portion of the message has ended and the IFR portion has begun.
The RxIFR interrupt is cleared when the received IFR byte is read from the BDLC Data Register. Once this is done, no further CPU
intervention is necessary until the next IFR byte is received, and this step is repeated. As with a message reception, all bytes of the
IFR, including the CRC byte, will be placed into the BDLC Data Register as they are received for the CPU to retrieve.
• When an EOF is Received, the IFR (and Message) is Complete
Once all IFR bytes (including the possible CRC byte) have been received from the bus, the bus will again be idle for a time period
equal to an EOD symbol. Following this, the BDLC module will determine whether or not the last byte of the IFR is a CRC byte,
and if so verify that the CRC byte is correct. If the CRC byte is not correct, this will be reflected in the BDLC State Vector Register.
After an additional period of time the EOD symbol will transition into an EOF symbol. When the EOF is received it will be reflected
in the BDLC State Vector Register, indicating to the user that the IFR, and the message, is complete.