Freescale Semiconductor MPC5200B - Manual (Page 399)

MPC5200B Users Guide, Rev. 1
11-34 Freescale Semiconductor
ATA Bus Background
Figure 11-8. Flow Diagram—DMA Command Protocol
Host:
BSY = 0 &
DRQ = 0
No
Host:
BSY = 0 &
DRQ = 0
No
Yes
Yes
Drive:
Error
Yes
No
Drive:
Transfer
Done
Drive:
Error
Drive:
nIEN = 0
No
Yes
No
Yes
No
Yes
Write Command Code
to Command register
Write Control/Command block
registers to setup data transfer
Drive: Set BSY = 1 and
begin command execution
Host: Read Status or
Alternate Status register
Host: Write Device/Head
register to select drive
Host: Read Status register
Host: Read Status or
Alternate Status register
Drive: Assert DMARQ when
ready to transfer data
Drive: Negate INTRQ
Host: Read Status register
Drive: Assert INTRQ
Drive: Clear BSY = 0 and DRQ = 0
Drive: Set error status
Host: Assert DMACK when
ready to transfer data
START
END
Drive: Set BSY = 1, or
BSY = 0 & DRQ = 1