Freescale Semiconductor MPC5200B - Manual (Page 614)

Functional Description
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 17-13
Figure 17-5. Baud Rate Divisor Equation
17.4.6 Special Features
17.4.6.1 SS Output
The SS output feature automatically drives the SS pin low during transmission to select external devices and drives it high during idle to
deselect external devices. When SS output is selected, the SS output pin is connected to the SS input pin of the external device.
The SS output is available only in master mode during normal SPI operation by asserting SSOE and SPIDDR bit 4 as shown in Table 17-3 .
The mode fault feature is disabled while SS output is enabled.
NOTE
Care must be taken when using the SS output feature in a multimaster system since the mode fault
feature is not available for detecting system errors between masters.
17.4.6.2 Bidirectional Mode (MOMI or SISO)
The bidirectional mode is selected when the SPC0 bit is set in SPI control register 2 (Table 17-12. Normal Mode and Bidirectional Mode).
In this mode, the SPI uses only one serial data pin for the interface with external device(s). The MSTR bit decides which pin to use. The MOSI
pin becomes the serial data I/O (MOMI) pin for the master mode, and the MISO pin becomes serial data I/O (SISO) pin for the slave mode
The MISO pin in the master mode and MOSI pin in the slave mode become general-purpose I/O.
The direction of each serial I/O pin depends on the corresponding data direction register bit If the pin is configured as an output, serial data
from the shift register is driven out on the pin. The same pin is also the serial input to the shift register.
If the pin is configured as an input, serial data from the shift register is discarded, but the external serial data through the pin is the serial input
to the shift register.
The SCK is output for the master mode and input for the slave mode.
The SS is the input or output for the master mode, and it is always the input for the slave mode.
The bidirectional mode does not affect SCK and SS functions; however, the SPIDDR bit 7 is not cleared by the mode fault error in the
bidirectional mode.
Table 17-12. Normal Mode and Bidirectional Mode
When SPE = 1 Master Mode MSTR = 1 Slave Mode MSTR = 0
Normal Mode
SPC0 = 0
Bidirectional Mode
SPC0 = 1
BaudRateDivisor SPPR 1 + ( ) 2 • SPR 1 + ( )
=
SPI
MOSI
MISO
SPIDDR 6
Serial Out
Serial In
SWOM enables open drain output.
(DDR1)
SPI
MOSI
MISO
Serial In
Serial Out
SPIDDR 7
SWOM enables open drain output.
(DDR0)
SPI
MOMI
SPI port
SPIDDR 6
Serial Out
Serial In pin 0
SWOM enables open drain output.
SPI port pin 7 becomes general-purpose I/O.
(DDR1)
SPI
SISO
SPIDDR 7
Serial In
Serial Out
SPI port
pin 1
SWOM enables open drain output.
SPI port pin 6 becomes general-purpose I/O.
(DDR0)