Freescale Semiconductor MPC5200B - Manual (Page 543)

MPC5200B Users Guide, Rev. 1
15-32 Freescale Semiconductor
PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00
13 Cell2xClk Codec —Cell Slave 2x Clock Frequency - takes effect only when bit 12 CellSlave = 1
0 = PSC Mclk frequency = Bit Clock from PSC1 master
1 = PSC Mclk frequency = 2x the Bit Clock from PSC1 master
other Modes—Reserved
14 ESAI Codec—Enhanced Serial Audio Interface
0 = PSC doesn’t support the ESAI mode.
1 = PSC support the ESAI mode. This mode allows the PSC to send and receive more the
one data word per frame, if the frame length is greater than the word length. The PSC send
only complete data words.
other Modes—Reserved
15 EnAC97 Codec —Enhanced AC97 mode - takes effect only when the AC97 mode is selected
(SIM = 0x3)
0 = No effect
1 = If the AC97 mode was selected the PSC use the “Enhanced AC97” mode to transmit
and receive the data.
other Modes—Reserved
16 SPI Codec—SPI mode
0 = PSC does not behave like an SPI
1 = PSC behaves like an SPI
other Modes—Reserved
17 MSTR Codec—SPI Master mode - takes effect only when bit SICR [SPI mode] = 1
0 = PSC behaves as an SPI slave
1 = PSC behaves as an SPI master
other Modes—Reserved
18 CPOL Codec—SPI Clock Polarity - takes effect only when bit SICR [SPI mode] = 1
This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI
modules, the SPI modules must have identical CPOL values
0 = Active-low clocks selected; SCK idles high
1 = Active-high clocks selected; SCK idles low
other Modes—Reserved
19 CPHA Codec—SPI Clock Phase
This bit is used to shift the SCK serial clock.To transmit data between SPI modules, the SPI
modules must have identical CPHA values
0 = data transfer starts which assertion of SS
1 = data transfer starts with the first edge of SCK
other modes—Reserved
20 UseEOF Codec—Use End-of-Frame flag takes effect only when bit 16 SPI mode = 1
0 = either 1, 2 or 4 bytes are transferred while Slave Select (SS) is held low, as determined
by Codec8, Codec16, Codec24 or Codec32 being selected by SICR[SIM]
1 = multiple bytes are transferred while maintaining SS low, up to and including the next
byte read from the Tx FIFO that has its EOF flag set
other modes—Reserved
Bit Name Description