Freescale Semiconductor MPC5200B - Manual (Page 637)

MPC5200B Users Guide, Rev. 1
18-20 Freescale Semiconductor
Transfer Initiation and Interrupt
18.5.3 Special Note on AKF
A new status bit has been added to MSR[4] for the MPC5200B release of this chip. The reason for this is that the legacy I2C module was
found to violate, in a merely academic sense, the I2C specification by sending out a very short 9th clock pulse after losing arbitration to another
master. According to the I2C specification, the losing I2C master may only complete “one byte’s worth” of clock pulses after losing
arbitration. The extra short 9th clock pulse driven by the losing I2C master was deemed to violate spec, so a fix to the module was performed
to bring the module in line with spec. One “side-effect” of this fix s that for the unique situation when the I2C module both loses arbitration
(AL) and is addressed as slave (AAS), the newly fixed I2C module generates two interrupt (IF) requests: one on the rising edge of the
acknowledge clock pulse (which is a new time to make the interrupt request) as well as on the falling edge of the acknowledge clock pulse
(which is the legacy time to do so). In order to help the software programmer distinguish the first interrupt request (which is non-legacy) from
the second interrupt request (which is legacy), the AKF bit was added. The AKF bit will be set only for the 2nd interrupt. The software
programmer may thus use the value of AKF (in addition to all the usual bits the software checks) to determine when to act. The following
figure on typical software flow for I2C routines will illustrate clearly how the AKF bit may be used.