Freescale Semiconductor MPC5200B - Manual (Page 357)

MPC5200B Users Guide, Rev. 1
10-60 Freescale Semiconductor
Functional Description
The Communication Sub-System Initiator Interface consists of Receive and Transmit FIFOs, integrated as separate Multi-Channel DMA
peripherals. Therefore, it is generally controlled by the Multi-Channel DMA controller through a pre-described program loop. As with all
Communication Sub-System peripherals, it can be accessed and controlled directly through the Slave bus interface if desired, but this path
does not generally lend itself to high throughput.
The Transmit and Receive FIFOs are 512 bytes deep and support PCI bursts up to 8 beats, each beat being a 32 bit word. The burst size is
programmable. The general approach is to write a PCI command and address to the control register along with the number of bytes to be
transmitted (Packet_Size).
When transmitting data, the module will wait for the Transmit FIFO to fill at least to the minimum number of bytes required to perform the
programmed burst; then it begins transmitting the data onto the PCI bus. Multi-Channel DMA must handle filling the Transmit FIFO to
support the specified number of bytes. Transmission will continue until the specified number of bytes have been sent.
When reading data, the module will check that enough space is available in the Receive FIFO and immediately begin PCI read transactions.
Multi-Channel DMA must handle emptying the Receive FIFO to support the specified number of bytes. Transmission will continue until the
specified number of bytes have been received. To avoid stale data while receiving the last burst flushing of the RX FIFO can be forced with
the set of the flush bit FE.
Section 10.3.3.2.4, Rx Enables PCIRER (RW) —MBAR + 0x388C
At this point, software must restart the procedure by at least re-writing the Packet_Size register. Each transmission of the specified number of
bytes is considered a “packet”. A new packet can be instructed to continue at the last valid PCI address or software may choose to write a new
starting address. The largest burst size is 8 PowerPC words and the largest Packet_Size is 4 Gbytes, so a packet will typically consist of many
PCI data bursts.
The Transmit Controller will wait until sufficient bytes are in the Transmit FIFO to support a full burst and will continue in this mode until
the entire packet is transmitted. Similarly, the Receive Controller will stall until sufficient space is available in the Receive FIFO to support a
full burst. If the packet is nearly done and the number of bytes remaining to complete the packet is less than Max_beats, the remaining data
will be performed as single-beat PCI transactions.
10.4.6.1 Access Width
This Multi-Channel DMA module primarily performs 32-bit data accesses to and from PCI, even though some signals are referred to in bytes.
The two least significant bits of the PCITPSR and PCIRPSR value are ignored. All PCI byte enables are enabled during these types of
accesses. Additionally, the FIFOs should only be accessed using 32-bit accesses.
The Communication Sub-System interface optionally supports 16 bit accesses on the PCI bus. Since reads and writes to and from the FIFO
require 32-bit accesses, using this option requires padding the remaining 16 bits of data.
10.4.6.2 Addressing
The Communication Sub-System Initiator interface does not use the addressing windows that are set up for the XL bus Initiator Interface.
Instead, the Tx Start Address register and Rx Start Address register are used. Software programs these registers with the initial starting address
for the packet. The module contains an internal counter which will present the incremented PCI address at the beginning of each successive
burst for packet transfers.
10.4.6.3 Data Translation
The PCI bus is inherently little endian in its byte ordering. The Comm bus however is big endian. Table 10-13 shows the byte lane mapping
between the two buses. Since this interface only allows 32-bit accesses, there is only one entry.
10.4.6.4 Initialization
The following list is the recommended procedure for setting up either the Transmit or Receive controller.
1. Set the Start Address
Table 10-13. Comm bus to PCI Byte Lanes for Memory
a
Transactions
a The byte lane translation will be similar for other types of transactions. However, the PCI address may be dif-
ferent as explained in
Section 10.4.1.5, Addressing .
Transfer
Comm bus PCI data bus
cAddress
[1:0]
cByte
Enable
[3:0]
Data Bus
PCI_
AD
[1:0]
BE
[3:0]
Data Bus
31:
24
23:
16
15:8 7:0 31:24 23:16 15:8 7:0
long 00 1111 OP0 OP1 OP2 OP3 00 0000 OP3 OP2 OP1 OP0