Freescale Semiconductor MPC5200B - Manual (Page 574)

PSC Operation Modes
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 15-63
Figure 15-15. PSC - AC97 Interface
Figure 15-16 shows the Timing diagram for the AC97 interface. For more AC97 Controller interface information, see the Audio Codec’97
Component Specification.
Figure 15-16. Timing Diagram—AC97 Interface
15.3.3.2 Generate a reset pulse for the external AC97 Codec device
The follow sequence generate a reset pulse for the external AC97 device:
1. Res line is high, after power up
2. write 0x02 to the OP1 register - Res line goes low
3. write 0x02 to the OP0 register - Res line goes high
NOTE
Some AC97 devices goes to a test mode, if the Sync line is high during the Res line is low (reset
phase). To avoid this behavior the Sync line must be also forced to zero during the reset phase. To do
that, the pin muxing should switch to GPIO mode and the GPIO control register should be used to
control the output lines.
15.3.3.3 AC97 Low-Power Mode
A General-Purpose I/O (GPIO) must be used as an AC97 reset output pin. PSC1 (or PSC2) monitors the first three time slots of each Tx
frame to detect the power-down condition for the AC97 digital interface. The power-down condition is detected as follows:
1. The first 3 bits of slot 1 must be set, indicating Tx frame and slots 1 and 2 are valid.
2. Slot 2 holds the power-down register (0x26) address in the external AC97 device.
3. Slot 3 has “1” in the fourth bit (bit 12/PR4 in power-down register 1), as defined in the AC97 specification.
Sync
BitCLK
SDATA_OUT
PSC1/PSC2
RES RESET
BIT_CLK
SDATA_IN
FRAME SYNC
SDATA_OUT
AC97 Codec
SDATA_IN
AC97 Controller
CLK
Frame
TxD
RxD
bit1 bit2 bit13 bit16
Slot 2 Slot 3 Slot 13 Slot 1
Slot 1
20 bits 20 bits bit14 bit15
Frame
Slot 2 Slot 3 Slot 13 Slot 1
Frame Sync Frame Sync
20 bits
bit1 bit2 bit13 bit16 20 bits 20 bits bit14 bit15 20 bits