6 fec rx fifo write pointer register-mbar + 0x31a0, 7 fec reset control register-mbar + 0x31c4, Fec reset control register—mbar + 0x31c4 -33 – Freescale Semiconductor MPC5200B User Manual
Page 498: Fec rx fifo write pointer register -33, Fec reset control register -33, Section 14-37, fec rx fifo write pointer register, Section 14-38, fec reset control register, 0x31, Table 1-1
FEC Tx FIFO Status Register—MBAR + 0x31A8
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
14-33
14.8.6
FEC Rx FIFO Write Pointer Register—MBAR + 0x31A0
FEC Tx FIFO Writer Pointer Register—MBAR + 0x31C0
The RFIFO_WRPTR and TFIFO_WRPTR are a FIFO-maintained pointer which point to the next FIFO location to be written. The write
pointer can be both read and written.
14.8.7
FEC Reset Control Register—MBAR + 0x31C4
The RESET_CNTRL register allows reset of the FIFO controllers.
Table 14-37. FEC Rx FIFO Write Pointer Register
FEC Tx FIFO Write Pointer Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
WRITE[9:0]
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0:21
—
Reserved
22:31
WRITE[9:0]
WRITE Pointer.
This pointer indicates the next location to be written by the FIFO controller.
Table 14-38. FEC Reset Control Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
RCT
L[1]
RCT
L[0]
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
W
RESET
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 1-1.
Bits
Name
Description
0:5
—
Reserved
6
RCTL[1]
0 = Do not Reset FIFO controllers.
1 = Reset FIFO controllers.