Freescale Semiconductor MPC5200B - Manual (Page 620)

I 2 C Controller
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 18-3
The master terminates communication by generating a STOP signal, which frees the bus. The master can generate a STOP even if the slave
has generated an acknowledge, at which point the slave must release the bus.
The master can generate a START signal followed by a calling command without generating a STOP signal first. This is called repeated
START.
18.2.2.1 Slave Address Transmission
The first byte of data transfer immediately after a START signal is the slave address transmitted by the master. This is a 7-bit calling address
followed by a R/
W bit. The R/ W bit tells the slave the desired direction of data transfer.
• 0 = Write transfer
• 1 = Read transfer
Only a slave with a calling address matching the address transmitted by the master will respond by sending back an acknowledge bit. This is
done by pulling SDA low at the 9th clock. See Figure 17 - 2.
Figure 18-2. Timing Diagram—Start, Address Transfer and Stop Signal
18.2.2.2 Data Transfer
Data transfer proceeds Byte-by-Byte in a direction specified by the R/
W
bit sent by the calling master. Each data byte is 8bits long. Data may
be changed only while SCL is low and must be held stable while SCL is high.
There is one clock pulse on SCL for each data bit. The MSB is transferred first. Each data byte must be followed by an acknowledge bit, which
is signalled from the receiving device by pulling SDA low at the 9th clock. One complete data byte transfer needs nine clock pulses. See
Figure 18-3 .
Figure 18-3. Timing Diagram—Data Transfer
18.2.2.3 Acknowledge
Figure 18-4 shows the transmitter releases the SDA line HIGH during the acknowledge clock pulse. The receiver pulls the SDA line low
during the acknowledge clock pulse so that it remains stable LOW during the clock pulse high period.
If a slave-receiver does not acknowledge the byte transfer, SDA must be left HIGH by the slave. The master then generates a STOP condition
to abort the transfer.
If a master-receiver does not acknowledge the slave transmitter after a byte transmission, it means End-Of-Data (EOD) to the slave. The slave
then releases the SDA line for the master to generate a STOP or START signal.
Bit5 Bit4 Bit3 Bit6 Bit2 Bit1 Bit0(R/W) Bit7 SDA
SCL
1 2 3 4 5 6 7 8 9
Start
MASTER drives data and clock lines
Ack Bit Stop
Master Release data
Slave drives Low
Slave
Release data
Bit5 Bit4 Bit3 Bit6 Bit2 Bit1 Bit0 Bit7 SDA
SCL 1 2 3 4 5 6 7 8 9
Start Stop
Bit5 Bit4 Bit3 Bit6 Bit2 Bit1 Bit0(R/W) Bit7
1 2 3 4 5 6 7 8 9
No Ack Bit
Slave Address DATA
Acknowledgement
From Receiver
SCL held low while
Interrupt is serviced
Interrupt Bit Set
(Byte Complete)