Freescale Semiconductor MPC5200B - Manual (Page 615)

MPC5200B Users Guide, Rev. 1
17-14 Freescale Semiconductor
Functional Description
17.4.7 Error Conditions
The SPI has two error conditions:
• Write collision error
• Mode fault error
17.4.7.1 Write Collision Error
The WCOL status flag in the SPI status register indicates that a serial transfer was in progress when the MCU tried to write new data into the
SPI data register. The following list explains valid write times (reference Table 17-3 and Table 17-4 for definitions of tT and tI).
• In Master Mode, a valid write is defined as any write within tI (when SS is high).
• In Slave Phase 0, a valid write is defined as any write within tI (when SS is high).
• In Slave Phase 1, a valid write is defined as any write within tT or tI (after last SCK edge to when SS goes low) excluding the first
two module clocks after the last SCK edge (beginning of tT is an illegal write).
A write during any other time will result in a WCOL error. The MCU write is disabled to avoid writing over the data being transmitted. No
interrupt is generated because the error status flag can be read upon completion of the transfer that was in progress at the time of the error.
This flag is cleared automatically by a read of the SPI status register (with WCOL set) followed by a read or write access to the SPI data
register.
17.4.7.2 Mode Fault Error
If the SS input becomes low while the SPI is configured as a master, it indicates a system error where more than one master may be trying to
drive the MOSI and SCK lines simultaneously. This condition is not permitted in normal operation; the MODF bit in the SPI status register
is set automatically.
In the special case where SPIDDR bit 4 is set, the SS pin is either a general-purpose output pin or SS output pin rather than being dedicated
as the SS input for the SPI system. In this special case, the mode error function is inhibited and MODF remains cleared.
When a mode fault error occurs, the SPE and MSTR bits are cleared and data direction bits controlling the output enable for the SCK, MISO,
and MOSI (or MOMI) pins are cleared. This forces those pins to be high impedance inputs to avoid any possibility of conflict with another
output driver.
If the mode fault error occurs in the bidirectional mode, the data direction bit associated with MISO (SISO) is not affected, since this bit is
dedicated for general purpose.
This flag is cleared automatically by a read of the SPI status register (with MODF set) followed by a write to SPI control register 1.
17.4.8 Low Power Mode Options
17.4.8.1 SPI in Run Mode
In run mode with the SPI system enable (SPE) bit in the SPI control register clear, the SPI system is in a low-power, disabled state. SPI
registers can still be accessed, but clocks to the core of this module are disabled. Since the SPI does not support other user modes (such as
supervisory), any configurations to those modes will cause the SPI to act as it does in normal run mode. The supported modes are run, wait,
and stop.
17.4.8.2 SPI in Wait Mode
SPI operation in wait mode depends upon the state of the SPISWAI bit in SPI control register 2.
• If SPISWAI is clear, the SPI operates normally when the CPU is in wait mode
• If SPISWAI is set, SPI clock generation ceases and the SPI module enters a power conservation state when the CPU is in wait mode.
— If SPISWAI is set and the SPI is configured for master, any transmission and reception in progress stops at wait mode entry.
The transmission and reception resumes when the SPI exits wait mode.
— If SPISWAI is set and the SPI is configured as a slave, any transmission and reception in progress continues if the SCK
continues to be driven from the master. This keeps the slave synchronized to the master and the SCK.
— If the master transmits several bytes while the slave is in wait mode, the slave will continue to send out bytes consistent with
the its operation mode at the start of wait mode (i.e. If the slave is currently sending its SPIDR to the master, it will continue
to send the same byte. Else if the slave is currently sending the last received byte from the master, it will continue to send each
previous master byte).