Freescale Semiconductor MPC5200B - Manual (Page 616)

Functional Description
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor 17-15
NOTE
Care must be taken when expecting data from a master while the slave is in wait or stop mode. Even
though the shift register will continue to operate, the rest of the SPI is shut down (i.e. a SPIF interrupt
will not be generated until exiting stop or wait mode). Also, the byte from the shift register will not
be copied into the SPIDR register until after the slave SPI has exited wait or stop mode. A SPIF flag
and SPIDR copy is only generated if wait mode is entered or exited during a tranmission. If the slave
enters wait mode in idle mode and exits wait mode in idle mode, neither a SPIF nor a SPIDR copy
will occur.
17.4.8.3 SPI in Stop Mode
Stop mode is dependent on the system. The SPI enters stop mode when the module clock is disabled (held high or low). If the SPI is in master
mode and exchanging data when the MCU enters stop mode, the transmission is frozen until the MCU exits stop mode. After stop, data to and
from the external SPI is exchanged correctly. In slave mode, the SPI will stay synchronized with the master.
The stop mode is equivalent to the wait mode with the SPISWAI bit set except that the stop mode is not dependent on the SPISWAI bit.
17.4.9 SPI Interrupts
The Serial Peripheral Interface only originates interrupt requests. The following is a description of how the Serial Peripheral Interface makes
a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt priority are chip dependent.
17.4.9.1 MODF Description
MODF occurs when the master detects an error on the SS pin. The master SPI must be configured for the MODF feature (see Table 17-3. SS
Input/Output Selection). Once MODF is set, the current transfer is halted and the following bits are changed:
• SPE=0, The SPI automatically disables itself.
• MSTR=0, The master bit in SPICR1 resets.
The MODF interrupt is reflected in the status register MODF flag. Clearing the flag will also clear the interrupt. This interrupt will stay active
while the MODF flag is set. MODF has an automatic clearing process which is described in 17.3.4 SPI Status Register —MBAR + 0x0F05.
17.4.9.2 SPIF Description
SPIF occurs when the SPI receives/transmits the last SCK edge in a data transfer operation. Once SPIF is set, it does not clear until it is
serviced. SPIF has an automatic clearing process which is described in 17.3.4 SPI Status Register —MBAR + 0x0F05 In the event that the
SPIF is not serviced before the end of the next transfer (i.e. SPIF remains active throughout another transfer), the latter transfers will be ignored
and no new data will be copied into the SPIDR