Freescale Semiconductor MPC5200B User Manual
Page 652
Memory Map / Register Definition
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
19-13
Note: The MSCAN Receive Interrupt Enable Register is held in reset state when the initialization mode is active (INITRQ = 1
and INITAK = 1). This register is writable again as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0).
19.5.9
MSCAN Transmitter Flag Register (CANTFLG)—MBAR + 0x090C / 0x98C
Note: This register is held in the reset state when the initialization mode is active (INITRQ = 1 and INITAK = 1). This register is
writable again as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0).
Note: To insure data integrity, do not write to Tx buffer registers while the TXE flag is cleared
Read: Anytime
Write: Anytime for TXEx flags when not in Initialization Mode; write of “1” clears flag, write of ‘0’ is ignored.
4:5
TSTATE[1:0]
Transmitter Status Change Enable—bits control sensitivity level in which Tx state changes
cause CSCIF interrupts. Independent of the chosen sensitivity level, TSTATE flags still
indicate the actual Tx state and are only updated if no CSCIF interrupt is pending.
00 = Do not generate CSCIF interrupt caused by Tx state changes.
01 = Generate CSCIF interrupt only if transmitter enters or leaves “BusOff” state.
Discard other Tx state changes for generating CSCIF interrupt.
10 = Generate CSCIF interrupt only if transmitter enters or leaves “TxErr” or “BusOff”
state. Discard other Tx state changes for generating CSCIF interrupt.
11 = Generate CSCIF interrupt on all Tx state changes.
6
OVRIE
Overrun Interrupt Enable
0 = No interrupt request is generated from this event.
1 = An overrun event causes an overrun interrupt request
7
RXFIE
Receiver Full Interrupt Enable
0 = No interrupt request is generated from this event
1 = Rx buffer full (successful message reception) event causes Rx full interrupt request
Table 19-12. MSCAN Transmitter Flag Register
msb 0
1
2
3
4
5
6
7 lsb
R
Reserved
TXE[2:0]
W
RESET:
0
0
0
0
0
1
1
1
Bit
Name
Description
0:4
—
Reserved
5:7
TXE[2:0]
Transmitter Buffer Empty—flag indicates the associated Tx message buffer is empty, and
thus not scheduled for transmission. CPU must clear the flag after a message is set up in
the Tx buffer and is due for transmission. MSCAN sets flag after message is successfully
sent. Flag is also set by MSCAN when Tx request is successfully aborted due to a pending
abort request. If not masked, a Tx interrupt is pending while this flag is set.
Clearing a TxEx flag also clears the corresponding ABTAKx. When a TxEx flag is set, the
corresponding ABTRQx bit is cleared. When listen-mode is active TxEx flags cannot be
cleared and no transmission is started.
0 = associated message buffer full (loaded with message due for Tx)
1 = associated message buffer empty (not scheduled)
Bit
Name
Description