Freescale Semiconductor MPC5200B - Manual (Page 613)

MPC5200B Users Guide, Rev. 1
17-12 Freescale Semiconductor
Functional Description
signal is the output from the master. The SS line is the slave select input to the slave. The SS pin of the master must be either high or
reconfigured as a general-purpose output not affecting the SPI.
Figure 17-4. SPI Clock Format 1 (CPHA = 1)
When CPHA = 1, the SS line can remain active low between successive transfers (can be tied low at all times). This format is sometimes
preferred in systems having a single fixed master and a single slave that drive the MISO data line.
The SPI interrupt request flag (SPIF) is common to both the master and slave modes. SPIF gets set after the last SCK cycle in a data transfer
operation to indicate that the transfer is complete SPIF is cleared automatically when the SPI status register is read (with SPIF set) followed
by a read or write to the SPI data register. If the SPIE bit is set when the SPIF flag is set, a hardware interrupt is requested.
A warning flag (WCOL) is set if a write to the SPI data register is attempted while a transfer is in progress. This is a conflict since the write
would erroneously overwrite the current contents of the SPI serial shift register. If this situation arises, the write to the SPI data register is
inhibited so as not to disturb the transfer in progress, and the WCOL flag is set to indicate the error. No interrupt is generated by WCOL
because an interrupt comes at the end of the transfer that was in progress at the time of the error.
17.4.5 SPI Baud Rate Generation
Baud rate generation consists of a series of divider stages. Six bits in the SPI baud rate register (SPPR2, SPPR1, SPPR0, SPR2, SPR1, and
SPR0) determine the divisor to the SPI module clock which results in the SPI baud rate.
The SPI clock rate is determined by the product of the value in the baud rate preselection bits (SPPR2–SPPR0) and the value in the baud rate
selection bits (SPR2–SPR0). The module clock divisor equation is shown in Table 17-5.
When all bits are clear (the default condition), the SPI module clock is divided by 2. When the selection bits (SPR2–SPR0) are 001 and the
preselection bits (SPPR2–SPPR0) are 000, the module clock divisor becomes 4. When the selection bits are 010, the module clock divisor
becomes 8, etc.
When the preselection bits are 001, the divisor determined by the selection bits is multiplied by 2. When the preselection bits are 010, the
divisor is multiplied by 3, etc. See
Table 17-6 for baud rate calculations for all bit conditions, based on a 40 MHz SPI module clock. The two
sets of selects allows the clock to be divided by a non-power of two to achieve other baud rates such as divide by 6, divide by 10, etc.
The baud rate generator is activated only when the SPI is in the master mode and a serial transfer is taking place. In the other cases, the divider
is disabled to decrease IDD current
t
L
t
T
for t
T
, t
l
, t
L
Minimum 1/2 SCK
t
I
t
L
If ne
xt tr
ansf
e
r beg
ins here
Begin End
SCK (CPOL = 0)
SAMPLE I
CHANGE O
SEL SS (O)
Transfer
SCK (CPOL = 1)
MSB first (LSBFE = 0):
LSB first (LSBFE = 1): MSB
LSB
LSB
MSB
Bit 5
Bit 2 Bit 6
Bit 1 Bit 4
Bit 3 Bit 3
Bit 4 Bit 2
Bit 5 Bit 1
Bit 6
CHANGE O
SEL SS (I)
MOSI pin
MISO pin
Master only
MOSI/MISO
t
L
= Minimum leading time before the first SCK edge
t
T
= Minimum trailing time after the last SCK edge
t
I
= Minimum idling time between transfers (minimum SS high time)
t
L
, t
T
, and t
I
are guaranteed for the master mode and required for the slave mode.