Freescale Semiconductor MPC5200B - Manual (Page 249)

MPC5200B Users Guide, Rev. 1
8-16 Freescale Semiconductor
Functional Description
8.4.2 Block Diagram
Figure 8-2 shows the SDRAM MC block diagram. It is important to notice:
• the internal XL bus is 64 bits wide
• the external interface to the SDRAM is only 32 bits wide
The SDRAM row, column, and bank address bits are extracted from internal address XLA[4:29]; XLA[29:31], TSIZ[0:2], and TBST control
the data path (MDQ, DQM).
Figure 8-2. Block Diagram—SDRAM Memory Controller
8.4.3 Transfer Size
All SDRAMs are “burst oriented” for read and write operations. The memory will move a full burst of data for every Read and Write command
unless the command is interrupted by a new command, explicitely terminated, or the data is masked. (Data mask does not shorten the
command, it only inhibits data capture.) The Memory Controller can interrupt certain commands, by supporting the explicit Burst Terminate
command.
The Memory Controller supports Burst and Non-Burst, or Single, transfers corresponding to the homonymous XL bus transfer types. A Burst
transfer is a 32 Byte block, 4 XLB data beats (8 memory data beats), spanning a modulo 32 address range. The starting address can be any
CS
ADDR[4:29]
A_CS
Sel
CS[1:0]
A[12:0]
BA[1:0]
Col
Bk
Row
Address
Pipeline
Latches
Col
Bk
Row
Address
Input
MUX
Address
Output
MUX
RAS
CAS
WE
DQSOUT
DQM[3:0]
CKE
OUT_EN[3:0]
DIN[0:63]
DOUT[0:63]
MDOUT[31:0]
MDIN[31:0]
SDRAM
Memory Controller
Write Data Buffer
Read Data Buffer
MUX
State Machine
Internal XL
bus
External Interface
Internal XL bus
DQSIN
ADDR[30:31]
D_CS
TSIZ[0:2]
TBST
Note: For 16-Bit External Data Width,
mem_ps = 1, only MDOUT[31:16] and
MDIN[31:16] shouldbe connected to
the external memories.