Freescale Semiconductor MPC5200B - Manual (Page 760)

MPC5200B Users Guide, Rev. 1
Freescale Semiconductor B-9
19.5.16 MSCAN Transmit Error Counter Register (CANTXERR)-MBAR + 0x091D/0x099D.................... 19-17
19.5.17 MSCAN ID Acceptance Registers (CANIDAR0-7)—MBAR + 0x0920 / 0x09A0 .......................... 19-18
19.5.18 MSCAN ID Mask Register (CANIDMR0-7)—MBAR + 0x0928 / 0x09A8..................................... 19-20
Section 19.6.1 Identifier Registers (IDR0-3) ................................................................................................................... 19-24
19.6.2 Data Segment Registers (DSR0-7) ..................................................................................................... 19-24
19.6.3 Data Length Register (DLR) .............................................................................................................. 19-25
19.6.4 MSCAN Transmit Buffer Priority Register (TBPR)—MBAR + 0x0979 / 0x09F9........................... 19-25
19.6.5 MSCAN Time Stamp Register High (TSRH)—MBAR + 0x097C / 0x09FC.................................... 19-26
19.6.6 MSCAN Time Stamp Register Low (TSRL)—MBAR + 0x097D / 0x09FD .................................... 19-26
Section 20.7 Memory Map and Registers ....................................................................................................................... 20-5
20.7.3.1 BDLC Control Register 1 (DLCBCR1)—MBAR + 0x1300 ............................................................... 20-5
20.7.3.2 BDLC State Vector Register (DLCBSVR) - MBAR + 0x1300 ........................................................... 20-7
20.7.3.3 BDLC Control Register 2 (DLCBCR2) - MBAR + 0x1304 ................................................................ 20-8
20.7.3.4 BDLC Data Register (DLCBDR) - MBAR + 0x1305........................................................................ 20-12
20.7.3.5 BDLC Analog Round Trip Delay Register (DLCBARD) - MBAR + 0x1308 .................................. 20-12
20.7.3.6 BDLC Rate Select Register (DLCBRSR) - MBAR + 0x1309 ........................................................... 20-14
20.7.3.7 BDLC Control Register (DLCSCR) - MBAR + 0x130C................................................................... 20-15
20.7.3.8 BDLC Status Register (DLCBSTAT) - MBAR + 0x130D................................................................. 20-15
Section 21.8.1.1 Device ID Register ..................................................................................................................................... 21-8