Intel Extensible Firmware Interface - Manual (Page 431)

Protocols — PCI Bus Support
Version 1.10 12/01/02 12-13
//*******************************************************
// EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION
//*******************************************************
typedef enum {
EfiPciOperationBusMasterRead,
EfiPciOperationBusMasterWrite,
EfiPciOperationBusMasterCommonBuffer,
EfiPciOperationBusMasterRead64,
EfiPciOperationBusMasterWrite64,
EfiPciOperationBusMasterCommonBuffer64,
EfiPciOperationMaximum
} EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION;
EfiPciOperationBusMasterRead
A read operation from system memory by a bus master that is not capable of producing
PCI dual address cycles.
EfiPciOperationBusMasterWrite
A write operation to system memory by a bus master that is not capable of producing PCI
dual address cycles.
EfiPciOperationBusMasterCommonBuffer
Provides both read and write access to system memory by both the processor and a bus
master that is not capable of producing PCI dual address cycles. The buffer is coherent
from both the processor’s and the bus master’s point of view.
EfiPciOperationBusMasterRead64
A read operation from system memory by a bus master that is capable of producing PCI
dual address cycles.
EfiPciOperationBusMasterWrite64
A write operation to system memory by a bus master that is capable of producing PCI
dual address cycles.
EfiPciOperationBusMasterCommonBuffer64
Provides both read and write access to system memory by both the processor and a bus
master that is capable of producing PCI dual address cycles. The buffer is coherent from
both the processor’s and the bus master’s point of view.