Intel Extensible Firmware Interface - Manual (Page 897)

32/64-Bit UNDI Specification
Version 1.10 12/01/02 E-31
E.3.4.7 PXE_CONTROL
typedef PXE_UINT16 PXE_CONTROL;
// Setting this flag directs the UNDI to queue this command for
// later execution if the UNDI is busy and it supports command
// queuing. If queuing is not supported, a
// PXE_STATCODE_INVALID_CONTROL error is returned. If the queue
// is full, a PXE_STATCODE_CDB_QUEUE_FULL error is returned.
#define PXE_CONTROL_QUEUE_IF_BUSY 0x0002
// These two bit values are used to determine if there are more
// UNDI CDB structures following this one. If the link bit is
// set, there must be a CDB structure following this one.
// Execution will start on the next CDB structure as soon as this
// one completes successfully. If an error is generated by this
// command, execution will stop.
#define PXE_CONTROL_LINK 0x0001
#define PXE_CONTROL_LAST_CDB_IN_LIST 0x0000
E.3.4.8 PXE_FRAME_TYPE
typedef PXE_UINT8 PXE_FRAME_TYPE;
#define PXE_FRAME_TYPE_NONE 0x00
#define PXE_FRAME_TYPE_UNICAST 0x01
#define PXE_FRAME_TYPE_BROADCAST 0x02
#define PXE_FRAME_TYPE_FILTERED_MULTICAST 0x03
#define PXE_FRAME_TYPE_PROMISCUOUS 0x04
#define PXE_FRAME_TYPE_PROMISCUOUS_MULTICAST 0x05
E.3.4.9 PXE_IPV4
This storage type is always big endian (network order) not little endian (Intel order).
typedef PXE_UINT32 PXE_IPV4;
E.3.4.10 PXE_IPV6
This storage type is always big endian (network order) not little endian (Intel order).
typedef struct s_PXE_IPV6 {
PXE_UINT32 num[4];
} PXE_IPV6;
E.3.4.11 PXE_MAC_ADDR
This storage type is always big endian (network order) not little endian (Intel order).
typedef struct {
PXE_UINT8 num[32];
} PXE_MAC_ADDR;