Intel Extensible Firmware Interface - Manual (Page 481)

Protocols — PCI Bus Support
Version 1.10 12/01/02 12-63
//*******************************************************
// EFI_PCI_IO_PROTOCOL_OPERATION
//*******************************************************
typedef enum {
EfiPciIoOperationBusMasterRead,
EfiPciIoOperationBusMasterWrite,
EfiPciIoOperationBusMasterCommonBuffer,
EfiPciIoOperationMaximum
} EFI_PCI_IO_PROTOCOL_OPERATION;
EfiPciIoOperationBusMasterRead
A read operation from system memory by a bus master.
EfiPciIoOperationBusMasterWrite
A write operation to system memory by a bus master.
EfiPciIoOperationBusMasterCommonBuffer
Provides both read and write access to system memory by both
the processor and a bus master. The buffer is coherent from both
the processor’s and the bus master’s point of view.
Description
The EFI_PCI_IO_PROTOCOL provides the basic Memory, I/O, PCI configuration, and DMA
interfaces that are used to abstract accesses to PCI controllers. There is one
EFI_PCI_IO_PROTOCOL instance for each PCI controller on a PCI bus. A device driver that
wishes to manage a PCI controller in a system will have to retrieve the EFI_PCI_IO_PROTOCOL
instance that is associated with the PCI controller. A device handle for a PCI controller will
minimally contain an
EFI_DEVICE_PATH_PROTOCOL instance and an
EFI_PCI_IO_PROTOCOL instance.
Bus mastering PCI controllers can use the DMA services for DMA operations. There are three
basic types of bus mastering DMA that is supported by this protocol. These are DMA reads by a
bus master, DMA writes by a bus master, and common buffer DMA. The DMA read and write
operations may need to be broken into smaller chunks. The caller of
Map() must pay attention to
the number of bytes that were mapped, and if required, loop until the entire buffer has been
transferred. The following is a list of the different bus mastering DMA operations that are
supported, and the sequence of
EFI_PCI_IO_PROTOCOL interfaces that are used for each DMA
operation type.