Intel SDS2 User Manual
Page 136
Intel® Server Board SDS2
Errata Listing
Revision 1.2
Order Number: A85874-002
125
34. Peer-to-peer PCI transactions are not supported between the
CIOB-controlled 64-bit PCI bus and the legacy 32-bit PCI bus
controlled by the HE-SL north bridge
Problem:
Peer-to-peer PCI transactions are supported between the two peer CIOB-
controlled, 64-bit, 66MHz, 3.3V PCI busses. Peer-to-peer PCI transactions are
not supported between the CIOB-controlled 64-bit, 66MHz, 3.3V PCI bus and
the legacy 32-bit, 33MHz, 5V PCI bus, which is controlled by the HE-SL north
bridge.
This information is not officially documented in ServerWorks datasheets or
confidential chipset documents.
Implication:
PCI adapter card transactions between 64-bit PCI bus and the 32-bit PCI bus
will fail.
Workaround:
Peer-to-peer PCI transactions must use the 64-bit buses controlled by the
CIOB.
Status:
NoFix.
35. SDS2 PCI slot current levels supported by the 5V rail
Problem:
The SDS2 server board is capable of supporting a maximum total of 21 amps
on the 5V rail to the six PCI slots on the server board.
Implication:
The SDS2 server board can support a maximum total of 21 amps on the 5V rail
to the six PCI slots on the server board. Integrators must consider this when
selecting PCI card configurations for use in the SDS2 server board.
Workaround:
Select PCI cards that utilize a combination of 3.3V and 5V voltage in order to
minimize the current utilized by the PCI cards on the 5V rail.
Status:
No Fix.
36. OB P100 NICs do not show at POST but attempt PXE boot and
appear in Boot Menu
Problem:
On board NIC are not displayed during post but do appear in Boot Device menu.
These controllers will also attempt to do a PXE boot if no other bootable devices
are found
.
Implication:
Not all boot devices displayed during POST when diagnostic display is enabled.
Workaround:
None. This is by design. The system BIOS builds the on-board network
controller Option ROM with an option that always makes the OPROM “quiet”. It