Intel SDS2 - Manual (Page 139)

Glossary Intel® Server Board SDS2
Revision 1.2
Order Number: A85874-002
II
Term Definition
Mux multiplexor
NMI Non-maskable Interrupt
OEM Original equipment manufacturer
Ohm Unit of electrical resistance
P32-A 32 bit PCI Segment
P64-B Full Length 64/66 MHz PCI Segment
P64-C Full Length 64/66 MHz PCI Segment
PBGA Pin Ball Grid Array
PCT Platform Confidence Test
PLD programmable logic device
PMI Platform management interrupt
POST Power On Self Test
RAM Random Access Memory
ROM Read Only Memory
RTC Real-time clock. Component of ICH peripheral chip on the baseboard.
SDRAM Synchronous Dynamic RAM
SEEPROM Serial electrically erasable programmable read-only memory
SEL System event log
SM Server Management
SMI Server management interrupt. SMI is the highest priority non-maskable interrupt.
SMM Server management mode.
SMS Server management software
SNMP Simple Network Management Protocol.
TBD To Be Defined
UART Universal a synchronous receiver and transmitter
USB Universal Serial Bus