Intel SDS2 - Manual (Page 17)

Intel® Server Board SDS2 Architecture
Revision 1.2
Order Number: A85874-002
3
• 64-bit, 66-MHz 3.3 V full-length PCI segment C (P64-C) with one embedded device
- Dual Channel Wide Ultra160 SCSI controller: Adaptec* AIC-7899W
- Two 64-bit 3.3 V Slots: PCI slots 5 and 6
• LPC (Low Pin Count) bus segment with two embedded devices
- Baseboard Management Controller (BMC) providing monitoring, alerting, and logging
of critical system information obtained from embedded sensors on the Server Board
- Super I/O controller chip providing all PC-compatible I/O (floppy, serial, keyboard,
mouse)
• X-Bus segment from CSB5 with one embedded device
- Flash ROM device for system BIOS: Fairchild* 29LV008B 8Mbit Flash ROM
• Two IDE connectors, supporting up to two ATA-100 compatible devices each. Note: Fab
4 board PBA A58285-402 and –403 supported only one IDE connector. Fab 5 PBA
A58285-502 (and later revisions) supports two IDE connectors.
• Four Universal Serial Bus (USB) ports: Three on the rear I/O and one on the Server
Board as a 10-pin header
• Two serial ports: One out to rear I/O and one through a 10-pin header on the Server
Board
• One floppy connector
• Four multi speed system fan connectors and two single speed CPU fan connectors.
• 34-pin SSI compliant front panel connector