I/o subsystem, 1 pci subsystem – Intel SDS2 User Manual
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Intel® Server Board SDS2
I/O Subsystem
Revision 1.2
Order Number: A85874-002
11
4. I/O Subsystem
4.1 PCI Subsystem
The primary I/O bus for SDS2 DP Server Board is PCI, with three PCI bus segments. The PCI
buses comply with the PCI Local Bus Specification, Rev 2.2. The P32-A bus segment is directed
through the HE-SL North Bridge while the two 64bit segments, P64-B and P64-C, are directed
through the CIOB20 I/O Bridge. The table below lists the characteristics of the three PCI bus
segments.
Table 4. PCI Bus Segment Characteristics
PCI Bus Segment
Voltage
Width
Speed
Type
PCI Slots
P32-A
5 V
32-bits
33-MHz
Peer Bus
Slots 3 and 4 – Full Length
P64-B
3.3 V
64-bits
66-MHz
Peer Bus
Slots 1 and 2 – Full Length
P64-C
3.3 V
64-bits
66-MHz
Peer Bus
Slots 5 and 6 – Full Length
Note: When an add-in 33-MHz PCI card is plugged into a P64 bus segment, such as in the P64-
C slot 5, this reduces the bus speed for all devices attached to that bus segment, including the
on-board SCSI controller.
4.1.1
32-bit, 33-MHz PCI Subsystem
All 32-bit, 33-MHz PCI I/O for the SDS2 Server Board is directed through the HE-SL North
Bridge. The 32-bit, 33-MHz PCI segment created by the HE-SL is called the P32-A segment. The
P32-A segment supports full-length, full-height PCI cards and contains the following embedded
devices and connectors:
•
2D/3D Graphics Accelerator: ATI RAGE XL Video Controller
•
Two Network Interface Controller: Intel 82550 Fast Ethernet Controller
•
PCI Slots 3 and 4
•
CSB5 South Bridge (PCI-to-LPC bridge)
Each of the embedded devices above, except for the CSB5 South Bridge, is allocated a GPIO to
disable the device.
4.1.1.1
Device IDs (IDSEL)
Each device under the PCI hub bridge has its IDSEL signal connected to one bit of AD [31:16],
which acts as a chip select on the PCI bus segment in configuration cycles. This determines a
unique PCI device ID value for use in configuration cycles. The following table shows the bit to
which each IDSEL signal is attached for P32-A devices, and corresponding device description.