Intel SHG2 - Manual (Page 90)

90 Intel Server Board SHG2 Product Guide
Table 8. Configuration Jumper (CN27)
Jumper Name Pins What it does at system reset
BIOS Write Protect 1-2 If these pins are jumpered, write protect is disabled allowing the BIOS boot
block to be updated. This feature is used in the rare case that a BIOS
update requires a BIOS boot block update as well. These pins should not
be jumpered for normal operation.
BMC Write Protect 3-4 If these pins are jumpered, write protect is disabled allowing the BMC boot
block to be updated. This feature is used in the rare case that a BIOS
update requires a BMC boot block update as well. These pins should not
be jumpered for normal operation.
Table 9. Configuration Jumper (CN53)
Jumper Name Pins What it does at system reset
PCIX1 DIS 1-2 Placing a jumper on pins 1-2 disables the 100 MHz PCI-X mode for the
CIOBX2 primary channel and forces the bus to run 66 MHz PCI. The
primary channel consists of Slot 1, Slot 2 and Gbit.
In the default configuration, pins 1-2 are not jumpered therefore the
primary channel is configured for 100 MHz PCI-X.
PCIX2 DIS 3-4 Placing a jumper on pins 3-4 disables the PCI-X mode for the CIOBX2
secondary channel and forces the bus to run 66 MHz PCI. The secondary
channel consists of Slot 6 and the on-board SCSI.
In the default configuration, pins 3-4 are jumpered therefore the secondary
channel is configured for 66 MHz PCI and on-board SCSI is enabled.
Enabling PCI-X on Slot 6 and Disabling On-board SCSI
✏
NOTE
Enabling the 133 MHz PCI-X on Slot 6 disables the on-board SCSI.
To enable the 133 MHz PCI-X on Slot 6, follow these instructions:
1. Enter BIOS setup.
2. While in BIOS setup, remove the jumper from CN53 pins 3-4.
3. In BIOS setup disable the on-board SCSI.
4. Select Save & Exit BIOS setup.
5. While the system is posting, shutdown the system by pushing the front panel power button.
6. While the system in off, plug a PCI-X card into Slot 6.
7. Push the front panel power button to power up the system.
8. Slot 6 is now 133 MHz PCI-X capable.