Intel D15343-003 - Manual (Page 102)

Intel
®
82854 Graphics Memory Controller Hub (GMCH)
102 D15343-003
4.11.3 PCICMD – PCI Command Register (Device #2)
This 16-bit register provides basic control over the IGD's ability to respond to PCI cycles. The
PCICMD register in the IGD disables the IGD PCI compliant master accesses to main system
memory.
Address Offset:
Default Value:
Access:
Size: 04-05h
0000h
Read Only, Read/Write
16 bits
Bit Description
15:10 Reserved
9 Fast Back-to-Back (FB2B)–RO
8 SERR# Enable (SERRE) –RO
7 Address/Data Stepping–RO
6 Parity Error Enable (PERRE) –RO
5 Video Palette Snooping (VPS) –RO
4 Memory Write and Invalidate Enable (MWIE) –RO
3 Special Cycle Enable (SCE) –RO
2 Bus Master Enable (BME) –R/W: This bit determines if the IGD is to function as a PCI compliant
master.
0= Disable IGD bus mastering (default).
1 = Enable IGD bus mastering.
1 Memory Access Enable (MAE) –R/W: This bit controls the IGD’s response to System Memory
Space accesses.
0= Disable (default).
1 = Enable.
0 I/O Access Enable (IOAE) –R/W: This bit controls the IGD’s response to I/O Space accesses.
0 = Disable (default).
1 = Enable.