Intel D15343-003 - Manual (Page 71)

Register Description
D15343-003 71
4.8.25 HEM – Host Error Control, Status, and Observation (Device #0)
Address Offset:
Default Value:
Access:
Size: F0-F3h
00000000h
Read Only, Read/Write
32 bits
Bit Description
31 Detected HADSTB1# Glitch (ASTB1GL): This bit is set when the GMCH has detected a glitch
on address strobe HADSTB1#. Software must write a 1 to clear this status bit.
30 Detected HADSTB0# Glitch (ASTB0GL): This bit is set when the GMCH has detected a glitch
on address strobe HADSTB0#. Software must write a 1 to clear this status bit.
29 Detected HDSTB3# Glitch (DSTB3GL): This bit is set when the GMCH has detected a glitch on
data strobe pair HDSTB3#. Software must write a 1 to clear this status bit.
28 Detected HDSTB2# Glitch (DSTB2GL): This bit is set when the GMCH has detected a glitch on
data strobe pair HDSTB2#. Software must write a 1 to clear this status bit.
27 Detected HDSTB1# Glitch (DSTB1GL): This bit is set when the GMCH has detected a glitch on
data strobe pair HDSTB1#. Software must write a 1 to clear this status bit.