4 pcists - pci status register, Pcists – pci status register, 4 pcists – pci status register – Intel D15343-003 User Manual
Page 75
Register Description
D15343-003
75
4.9.4
PCISTS – PCI Status Register
PCISTS is a 16-bit status register that reports the occurrence of error events on Device #0's PCI
Interface. Bit 14 is Read/Write Clear. All other bits are Read Only. Since GMCH Device #0 does
not physically reside on PCI_A, many of the bits are not implemented.
Address Offset:
Default Value:
Access:
Size:
06-07h
0080h
Read Only, Read/Write Clear
16 bits
Bit
Descriptions
15
Detected Parity Error (DPE):
The GMCH does not implement this bit and it is hardwired to a 0.
Writes to this bit position have no effect.
14
Signaled System Error (SSE):
The GMCH does not implement this bit and it is hardwired to a 0.
Writes to this bit position have no effect.
13
Received Master Abort Status (RMAS):
The GMCH does not implement this bit and it is
hardwired to a 0. Writes to this bit position have no effect.
12
Received Target Abort Status (RTAS):
The GMCH does not implement this bit and it is
hardwired to a 0. Writes to this bit position have no effect.
11
Signaled Target Abort Status (STAS):
The GMCH does not implement this bit and it is
hardwired to a 0. Writes to this bit position have no effect.
10:9
DEVSEL Timing (DEVT):
These bits are hardwired to “00”. Writes to these bit positions have no
affect. Device #0 does not physically connect to PCI_A. These bits are set to “00” (fast decode)
so that the GMCH does not limit optimum DEVSEL timing for PCI_A.
8
Master Data Parity Error Detected (DPD):
The GMCH does not implement this bit and it is
hardwired to a 0. Writes to this bit position have no effect.
7
Fast Back-to-Back (FB2B):
This bit is hardwired to 1. Writes to these bit positions have no
effect. Device #0 does not physically connect to PCI_A. This bit is set to 1 (indicating fast back-to-
back capability) so that the GMCH does not limit the optimum setting for PCI_A.
6:5
Reserved
4
Capability List (CLIST):
This bit is hardwired to 0 to indicate to the configuration software that
this device/function does not implement new capabilities.
Default Value = 0
3:0
Reserved