Intel D15343-003 - Manual (Page 143)

Functional Description
D15343-003 143
6.5.4 Interlace support for Video Overlay Window
In interlace mode, support for Field1 and Field2 timing generation is supported by the Video
Overlay. The Video Overlay makes use of the DPODPfieldID signal generated by the Pipe A
timing generator to synchronize the field timing. This signal is used to indicate which field should
be scanned out. The Video Overlay determines the correct lines to be used to assemble Field1 and
Field2 during on the fly up and down scaling. The Bob method is used to generate the missing
field information for Field2 when an interlaced source is used.
Table 32. DVO Control Data Bits
The Display Pipe A timing registers:
will hold data associated with physical buffer 0.
The Display Pipe B timing registers:
will hold data associated with physical buffer 1.
The start address of physical buffer 0 will be in DSPABASE and the start address of physical buffer
1 will be in DSPASEC. The stride for both buffers will be in DSPASTRIDE. Refer to
Section 4.0,
“Register Description” on page 41 for programming details.
After rising edge of
VSYNC
1st pixel clock 2nd pixel clock
DVOB [23] Buffer ID Buffer ID
DVOB [22:12] Undefined Horizontal image size
DVOB [10:0] Undefined Vertical image size
HTOTAL_A HBLANK_A HSYNC_A VTOTAL_A
VBLANK_A VSYNC_A PIPEASRC
HTOTAL_B HBLANK_B HSYNC_B VTOTAL_B
VBLANK_B VSYNC_B PIPEBSRC