Intel D15343-003 - Manual (Page 79)

Register Description
D15343-003 79
4.9.13 DRA – DRAM Row Attribute Register (Device #0)
The DDR SDRAM Row Attribute Register defines the page sizes to be used when accessing
different pairs of Rows. Each Nibble of information in the DRA registers describes the page size
of a pair of Rows:
Row 0, 1: 50h
Row 2, 3: 51h
52h-5Fh: Reserved.
Address Offset:
Default Value:
Access:
Size: 50-51h
77h
Read/Write
8 bits
7 6 4 3 2 0
R Row attribute for Row1 R Row Attribute for Row0
7 6 4 3 2 0
R Row attribute for Row3 R Row Attribute for Row2
Bit Description
7 Reserved
6:4 Row Attribute for odd-numbered Row: This field defines the page size of the corresponding row.
000: Reserved
001: 4 kB
010: 8 kB
011: 16 kB
111: Not Populated
Others: Reserved
3 Reserved
2:0 Row Attribute for even-numbered Row: This field defines the page size of the corresponding row.
000: Reserved
001: 4 kB
010: 16 kB
111: Not Populated
Others: Reserved