Intel D15343-003 - Manual (Page 91)

Register Description
D15343-003 91
15:12 Write Thermal Based Power Throttle Control (WTTC): These bits select the Thermal based
Power Throttle Bandwidth Limits for Write operations to system memory.
R/W, RO if Throttle Lock
0h = 85%
1h = 70%
2h = 65%
3h = 60%
4h = 55%
5h = 50%
6h = 45%
7h = 40%
8h = 35%
9h = 30%
Ah = 20%
B-Fh = Reserved
11 Counter Based Throttle Lock (CTLOCK): This bit secures RCTC and WCTC. This bit defaults
to 0. Once a 1 is written to this bit, RCTC and WCTC (including CTLOCK) become Read-Only.
10 Thermal Throttle Lock (TTLOCK): This bit secures the DDR SDRAM Throttling Control
register. This bit defaults to 0. Once a 1 is written to this bit, all of the configuration register bits
in DTC (including TTLOCK) except CTLOCK, RCTC and WCTC become Read-Only.
9 Thermal Power Throttle Control fields Enable :
0 = RTTC and WTTC are not used. RCTC and WTCT are used for both Counter and Thermal
based Throttling.
1 = RTTC and WTTC are used for Thermal based Throttling.
8 High Priority Stream Throttling Enable :
Normally High Priority Streams are not Throttled when either the counter based mechanism or
Thermal Sensor mechanism demands Throttling.
0 = Normal operation.
1 = Block High priority streams during Throttling.
7:0 Global DDR SDRAM Sampling Window (GDSW): This 8-bit value is multiplied by 4 to define
the length of time in milliseconds (0–1020) over which the number of Octal Words (16 bytes)
Read/Written is counted and Throttling is imposed. Note that programming this field to 00h
disables system memory throttling.
Recommended values are between 0.25 and 0.75 seconds.