Intel D15343-003 - Manual (Page 34)

Intel
®
854 Graphics Memory Controller Hub (GMCH)
34 D15343-003
DPMS I
DVO
Display Power Management Signaling: This signal is used only in
mobile systems to act as the DREFCLK in certain power management
states (i.e., Display Power Down Mode); DPMS Clock is used to
refresh video during S1-M. Clock Chip is powered down in S1-M.
DPMS should come from a clock source that runs during S1-M and
needs to be 1.5 V. So, an example would be to use a 1.5-V version of
SUSCLK from ICH4-M.
DAC Clocking
DREFCLK I
LVTTL
Display Clock Input: This pin is used to provide a 48-MHz input clock
to the Display PLL that is used for 2D/Video and DAC.