Jameco Electronics Rabbit 3000 - Manual (Page 191)

182 Rabbit 3000 Microprocessor
12.6 Clocked Serial Ports
Ports A–D can operate in clocked mode. The data line and clock line are driven as shown in
Figure 12-4. The data and clock are provided as 8-bit bursts with the LSB shifted out and/or
received first. By default the transmit shift register advances on the falling edge of the clock
and the receiver samples the data on the rising edge of the clock. The serial port can generate
the clock or the clock can be provided externally.
The clock polarity is programmable in clocked serial mode according to Figure . The clocked
serial transfer may also be synchronized to the output of either of the match conditions in
Timer B to give precisely timed transfers.
To enable the clocked serial mode, a code must be in bits (3,2) of the control register, enabling
the clocked serial mode with either an internal clock or an external clock. The transition
between the external and the internal clock should be performed with care. Normally a pullup
resistor is needed on the clock line to prevent spurious clocks while neither party is driving the
clock.
Figure 12-5. Clock Polarities Supported in Clocked Serial Mode
In clocked serial mode the shift register and the data register work in the same fashion as for
asynchronous communications. However, to initiate basic sending or receiving, a command
must be issued by writing to bits (7,6) of the control register for each byte sent or received.
One command is for sending a byte, a different command is for receiving a byte, and yet
another command can initiate a transmit and receive at the same time for full duplex commu-
nication. Alternatively, a read or write to the Serial Ports A-D Address registers (SxAR) elim-
inates the need to issue separate receive and transmit commands. In clocked serial mode,
reading the data from the corresponding SxAR register automatically causes the receiver to
start a byte receive operation, eliminating the need for software to issue the Start Receive
command. Any data contained in the receive buffer will be read first before being replaced
CLK (Mode 00)
Tx D0 D1 D2 D3 D4 D5 D6 D7
Rx D0 D1 D2 D3 D4 D5 D6 D7
CLK (Mode 10)
CLK (Mode 01)
CLK (Mode 11)