Jameco Electronics Rabbit 3000 - Manual (Page 305)

296 Rabbit 3000 Microprocessor
B.1.11 External I/O Improvements
Three new features have been added to the external I/O strobes: the ability to invert the
strobe signal, the ability to shorten a read strobe by one clock, and the ability to direct a
strobe to either the alternate I/O bus (if enabled) or the memory bus.
The new control bits for the external I/O strobes are listed in Table B-21.
NOTE: Bits [1:0] were always written with zero in the original Rabbit 3000 chip.
Table B-21. I/O Bank x Control Register
I/O Bank x Control Register (IB0CR) (Address = 0x0080)
(IB1CR) (Address = 0x0081)
(IB2CR) (Address = 0x0082)
(IB3CR) (Address = 0x0083)
(IB4CR) (Address = 0x0084)
(IB5CR) (Address = 0x0085)
(IB6CR) (Address = 0x0086)
(IB7CR) (Address = 0x0087)
Bit(s) Value Description
7:6 00 Fifteen wait states for accesses in this bank.
01 Seven wait states for accesses in this bank.
10 Three wait states for accesses in this bank.
11 One wait state for accesses in this bank.
5:4 00 The Ix signal is an I/O chip select.
01 The Ix signal is an I/O read strobe.
10 The Ix signal is an I/O write strobe.
11 The Ix signal is an I/O data (read or write) strobe.
3
0
Writes are not allowed to this bank. Transactions are normal in every other way;
only the write strobe is inhibited.
1 Writes are allowed to this bank.
2
0 Active-Low Ix signal.
1 Inverted (active-High) Ix.
1
0 Normal I/O Transaction timing.
1 Shorten read strobe by one clock cycle. Transaction length remains the same.
0
0 Use I/O bus if enabled.
1 Always use memory data bus.