NEC uPD78056Y - Manual (Page 500)

500
CHAPTER 21 INTERRUPT AND TEST FUNCTIONS
21.4.2 Maskable interrupt request acknowledge operation
A maskable interrupt request becomes acknowledgeable when an interrupt request flag is set to 1 and the interrupt
mask flag is cleared to 0. A vectored interrupt request is acknowledged in an interrupt enable state (with IE flag set
to 1). However, a low-priority interrupt request is not acknowledged during high-priority interrupt service (with ISP
flag reset to 0).
Table 21-3 shows the time from generation of maskable interrupt request to interrupt servicing.
For the interrupt request acknowledging timing, refer to Figure 21-14 and 21-15.
Table 21-3. Times from Maskable Interrupt Request Generation to Interrupt Service
Minimum Time Maximum Time Note
When
××
PR
×
=0 7 clocks 32 clocks
When
××
PR
×
=1 8 clocks 33 clocks
Note If an interrupt request is generated just before a divide instruction, the wait time is maximized.
Remark 1 clock : (fCPU: CPU clock)
If two or more maskable interrupt requests are generated simultaneously, the request specified for higher priority
with the priority specify flag is acknowledged first. If two or more requests are specified for the same priority with
priority specify flag, the interrupt request with higher default priority is acknowledged first.
Any reserved interrupt requests are acknowledged when they become acknowledgeable.
Figure 21-13 shows interrupt request acknowledge algorithms.
If a maskable interrupt request is acknowledged, the contents of acknowledged interrupt is saved in the stacks,
program status word (PSW) and program counter (PC), in that order, the IE flag is reset to 0, and the acknowledged
interrupt priority specify flag contents are transferred to the ISP flag. Further, the vector table data determined for
each interrupt request is loaded into PC and branched.
Return from the interrupt is possible with the RETI instruction.
f CPU
1