NEC uPD78056Y - Manual (Page 549)

549
CHAPTER 26
µ
PD78P054, 78P058
7
RAM2
Symbol
IMS
6
RAM1
5
RAM0
4
0
3
ROM3
2
ROM2
1
ROM1
0
ROM0
Address
FFF0H C8H
After
Reset
R/W
R/W
1
Internal ROM Capacity selection
32 Kbytes
ROM3
0
ROM2
0
ROM1
0
ROM0
Setting prohibited Other than above
Internal High-Speed RAM Capacity Selection RAM2 RAM1 RAM0
512 bytes 0 1 0
Setting prohibited Other than above
0
0
16 Kbytes
24 Kbytes
1
1
0
1
0
0
1024 bytes 1 1 0
Figure 26-1. Memory Size Switching Register Format (
µ
PD78P054)
The IMS settings to give the same memory map as mask ROM versions are shown in Table 26-3.
Table 26-3. Examples of Memory Size Switching Register Settings (
µ
PD78P054)
Relevant Mask ROM Version IMS Setting
µ
PD78052 44H
µ
PD78053 C6H
µ
PD78054 C8H
26.1 Memory Size Switching Register (
µ
PD78P054)
The
µ
PD78P054 allows users to define its internal ROM and high-speed RAM sizes using the memory size
switching register (IMS), so that the same memory mapping as that of a mask ROM version with a different-size internal
ROM and high-speed RAM is possible. IMS is set with an 8-bit memory manipulation instruction.
RESET input sets IMS to C8H.