Oki B4100 - Manual (Page 411)

40055101TH Rev.4 411 /
Figure A3.2.10 Interface between M17 Board and OPE (operation unit)
X'tal
MOS CPU
Internal ROM
Key switch
matrix
LCD unit
LEDs
IC1
Eight LEDs
KSCAN0
to
KSCAN7
KSENS0
to
KSENS7
DB0
to
DB7
Control signal
CN9 CN1
TXD
RXD
PSMODE
MPREQ
IRST
OPECHK
+5 V
GND
TXDOPE
RXDOPE
PSMODE
MPREQ
OPERST-N
OPECHK
+5 V
0 V
PCI-N
RIINT
HUP-N
1
2
3
4
5
13
14
15
6,7
8,9
M17 OPE
CPU
IOGA
IC2
ACON
MP/OFF
CN6 CN3
S
R
NCU M17
S
RP
R
CML
DP
SR
MUTE
PBXE
to OPE
to OPE
OH2
RI-N
A8, B8
A4, B4
A6, B6
A3
B3
A2
A1
B1, B2
A15
A14
Modem
CPU
IOGA
IC2
IC19
Relay driver circuit
Receiving
sensitivity
control
Hook-up signal
detection circuit
Ringing signal
detection circuit
Figure A3.2.9 Interface between M17 Board and NCU Board