Xilinx LogiCore PLB PCI Full Bridge - Manual (Page 12)

PLB PCI Full Bridge (v1.00a)
12 www.xilinx.com DS508 March 21, 2006
Product Specification
EARL
Y ACCESS
G50
Number of IDELAY
controllers instantiated.
Ignored it not Virtex-4
C_NUM_
IDELAYCTRL
2-6
(Virtex-4 only)
2 integer
G51
Includes IDELAY
primitive on GNT_N.
Set by tcl-scripts and
ignored if not Virtex-4.
C_INCLUDE_
GNT_DELAY
1=Include IDELAY
primitive
(Virtex-4 only)
0=No IDELAY primitive
0 integer
G52
Provides a means for
BSB to pass LOC
coordinates for
IDELAYCTRLs for a
given board to
EDK and is optional for
user to set LOC
constraints. This
parameter has no
impact on bridge
functionality.
C_IDELAY
CTRL_LOC
See Device
Implementation section,
subsection Virtex-4
Support for allowed
values
NOT_SET string
v3.0 Core Parameters Group
G53
PCI Configuration
Space Header Device
ID
C_DEVICE_ID 16-bit vector 0x0000
std_logic_
vector
G54
PCI Configuration
Space Header Vendor
ID
C_VENDOR_
ID
16-bit vector 0x0000
std_logic_
vector
G55
PCI Configuration
Space Header Class
Code
C_CLASS_
CODE
24-bit vector 0x000000
std_logic_
vector
G56
PCI Configuration
Space Header Rev ID
C_REV_ID 8-bit vector 0x00
std_logic_
vector
G57
PCI Configuration
Space Header
Subsystem ID
C_SUB
SYSTEM_ID
16-bit vector 0x0000
std_logic_
vector
G58
PCI Configuration
Space Header
Subsystem Vendor ID C_SUBSYSTE
M_VENDOR_
ID
16-bit vector 0x0000
std_logic_
vector
G59
PCI Configuration
Space Header
Maximum Latency
C_MAX_LAT 8-bit vector 0x0F
std_logic_
vector
G60
PCI Configuration
Space Header
Minimum Grant
C_MIN_GNT 8-bit vector 0x04
std_logic_
vector
Configuration
Table 1: PLB PCI Bridge Interface Design Parameters (Contd)
Generic
Feature /
Description
Parameter
Name
Allowable Values
Default
Value
VHDL
Type