Xilinx LogiCore PLB PCI Full Bridge - Manual (Page 27)

PLB PCI Full Bridge (v1.00a)
DS508 March 21, 2006 www.xilinx.com 27
Product Specification
EAR
LY
ACCESS
PLB PCI Bridge Reset Register Description
The IP Reset module is always instantiated in the PLB PCI Bridge. Details on the IPIF Reset module can
be found in the
Processor IP Reference Guide . The IP Reset module permits the software reset of the PLB
PCI Bridge, independently of other modules in the system. The MIR is not included.
23
PLB Master
Write Retry
Disconnect
Read/Write 0x0
PLB Master Burst Write Retry Disconnect Enable-
Enables this interrupt to be passed to the interrupt controller.
• 0 - Not enabled.
• 1 - Enabled.
24
PLB Master
Write Retry
Read/Write 0x0
PLB Master Write Retry Enable- Enables this interrupt to be
passed to the interrupt controller.
• 0 - Not enabled.
• 1 - Enabled.
25
PLB Master
Write Master
Abort
Read/Write 0x0
PLB Master Write Master Abort Enable- Enables this
interrupt to be passed to the interrupt controller.
• 0 - Not enabled.
• 1 - Enabled.
26
PLB Master
Write Target
Abort
Read/Write 0x0
PLB Master Write Target Abort Enable- Enables this
interrupt to be passed to the interrupt controller.
• 0 - Not enabled.
• 1 - Enabled.
27
PLB Master
Write PERR
Read/Write 0x0
PLB Master Write PERR Enable- Enables this interrupt to be
passed to the interrupt controller.
• 0 - Not enabled.
• 1 - Enabled.
28
PLB Master
Write SERR
Read/Write 0x0
PLB Master Write SERR Enable- Enables this interrupt to be
passed to the interrupt controller.
• 0 - Not enabled.
• 1 - Enabled.
29
PLB Master
Read Target
Abort
Read/Write 0x0
PLB Master Read Target Abort Enable- Enables this
interrupt to be passed to the interrupt controller.
• 0 - Not enabled.
• 1 - Enabled.
30
PLB Master
Read PERR
Read/Write 0x0
PLB Master Read PERR Enable- Enables this interrupt to be
passed to the interrupt controller.
• 0 - Not enabled.
• 1 - Enabled.
31
PLB Master
Read SERR
Read/Write 0x0
PLB Master Read SERR Enable- Enables this interrupt to be
passed to the interrupt controller.
• 0 - Not enabled.
• 1 - Enabled.
Table 9: Bridge Interrupt Enable Register Bit Definitions (Bit assignment assumes 32-bit bus) (Contd)
Bit(s) Name Access
Reset
Value
Description