Xilinx LogiCore PLB PCI Full Bridge - Manual (Page 26)

PLB PCI Full Bridge (v1.00a)
26 www.xilinx.com DS508 March 21, 2006
Product Specification
EARL
Y ACCESS
Bridge Interrupt Enable Register Description
The PLB PCI Bridge has interrupt enable features as described in IPSPEC048 PLB Device Interrupt
Architecture . Bit assignment in the Bridge Interrupt Enable Register is shown in Table 9 . The interrupt
enable register is read/write. All bits are cleared upon reset.
25
PLB Master
Write Master
Abort
Read/Write
1 to clear
0x0
PLB Master Write Master Abort- Interrupt(25) indicates
that the PLB PCI Bridge asserted a PCI master abort due to
no response from a target.
26
PLB Master
Write Target
Abort
Read/Write
1 to clear
0x0
PLB Master Write Target Abort- Interrupt(26) indicates a
PCI target abort occurred during a PLB Master Write to a
PCI target.
27
PLB Master
Write PERR Read/Write
1 to clear
0x0
PLB Master Write PERR- Interrupt(27) indicates a PERR
error is detected on a PLB Master write to a PCI target.
28
PLB Master
Write SERR Read/Write
1 to clear
0x0
PLB Master Write SERR- Interrupt(28) indicates that a
SERR error was detected by the v3.0 core when performing
as a PCI initiator writing data to a PCI target.
29
PLB Master
Read Target
Abort
Read/Write
1 to clear
0x0
PLB Master Read Target Abort- Interrupt(29) indicates
that a target abort was detected by the v3.0 core when
performing as a PCI initiator reading data from a PCI target.
30
PLB Master
Read PERR Read/Write
1 to clear
0x0
PLB Master Read PERR- Interrupt(30) indicates that a
PERR was detected by the v3.0 core when performing as a
PCI initiator reading data from a PCI target.
31
PLB Master
Read SERR Read/Write
1 to clear
0x0
PLB Master Read SERR- Interrupt(31) indicates that a
SERR error was detected by the v3.0 core when performing
as a PCI initiator reading data from a PCI target.
Table 9: Bridge Interrupt Enable Register Bit Definitions (Bit assignment assumes 32-bit bus)
Bit(s) Name Access
Reset
Value
Description
0-18 Read 0x0 Unassigned-
19
PCI Initiator
Write SERR
Read/Write 0x0
PCI Initiator Write SERR Enable- Enables this interrupt to
be passed to the interrupt controller.
• 0 - Not enabled.
• 1 - Enabled.
20
PCI Initiator
Read SERR
Read/Write 0x0
PCI Initiator Read SERR Enable- Enables this interrupt to
be passed to the interrupt controller.
• 0 - Not enabled.
• 1 - Enabled.
21 Reserved 0x0 • Reserved
22
PLB Master
Write Retry
Timeout
Read/Write 0x0
PLB Master Burst Write Retry Timeout Enable- Enables
this interrupt to be passed to the interrupt controller.
• 0 - Not enabled.
• 1 - Enabled.
Table 8: Bridge Interrupt Register Bit Definitions (Bit Assignment Assumes 32-bit Bus) (Contd)
Bit(s) Name Access
Reset
Value
Description