Xilinx LogiCore PLB PCI Full Bridge - Manual (Page 39)

PLB PCI Full Bridge (v1.00a)
DS508 March 21, 2006 www.xilinx.com 39
Product Specification
EAR
LY
ACCESS
burst write data from the PLB to PCI beyond the valid IPIF BAR address range. The PLB PCI Bridge
does not support fast back-to-back PCI transactions.
Abnormal Terminations
In the context of the PLB PCI bridge, cacheline transactions are special cases of a burst. Abnormal
terminations during a cacheline write operation have the same response as a burst write transaction.
Recall that the PLB IPIF specification requires that the targetword of a cacheline write be the first word
of the line.
• If a SERR error, including a parity error during the address phase, is detected on either a single or
burst transfer, the PLB Master Write SERR interrupt is asserted. If the PLB transfer is in progress,
Sl_MErr
is asserted with Sl_wrDAck.
• If on either a single or burst write the PLB PCI Bridge asserts a master abort due to no response
from a target, the PLB PCI Bridge asserts a PLB Master Write Master Abort interrupt. The IPIF2PCI
FIFO will be flushed when the Master Abort Write interrupt is asserted. If the PLB transfer is in
progress, Sl_MErr
is asserted with Sl_wrDAck.
• If on a single transfer or on the first data cycle of a burst transfer a PCI retry from the PCI target
occurs, the PLB PCI Bridge will automatically perform up to a parameterized number of retries.
The number of retries is set by C_NUM_PCI_RETRIES_IN_WRITES. A parameterized wait time
before a retry occurs is set by C_NUM_PCI_PRDS_BETWN_RETRIES_IN_WRITES. Both
parameters are set at build time. During the time retries are possible, subsequent PLB master write
operations to a PCI target will be inhibited by assertion of PLB rearbitrate. If the retries are not
successful (i.e., disconnects or more PCI retries occur), a PLB Master Write interrupt identifying the
failure mode will be asserted. The IPIF2PCI FIFO will be flushed upon asserting any of the three
PLB Master Write Retry interrupts. Consistent with the PCI Spec, the PLB master is required to
perform the write again if the last of the automatic retries was terminated with a PCI retry.
• If on a single transfer the target disconnects with data, the transfer will be completed.
• If the target disconnects, either with or without data after the first data phase of a burst transfer, the
IPIF/v3.0 core terminates the PCI transaction. If the IPIF2PCI FIFO is not empty, another PCI
transaction is attempted. Due to pipelining in the v3.0 core, the IPIF2PCI_FIFO must backup 1-3
words, depending on the type of target disconnect. The PLB PCI Bridge performs up to a
parameterized number of retries (C_NUM_PCI_RETRIES_IN_WRITES). A parameterized wait
time (C_NUM_PCI_PRDS_BETWN_RETRIES_IN_WRITES) before a retry occurs is included. Both
parameters are set at build time and are the same as defined for PCI retry situation. During the time
retries are in progress, subsequent PLB master write operations to a PCI target are inhibited. If the
PCI transaction retries are not successful due to any combination of PCI retries, disconnection, or
time out, a PLB Master Write Retry interrupt, PLB Master Write Retry Disconnect interrupt, or PLB
Master Write Retry Timeout interrupt, respectively, will be asserted. The actual interrupt that is
asserted is defined by the type of disconnect that occurred on the last of the prescribed number of
retries. The IPIF2PCI FIFO is flushed upon asserting one of the PLB Master Write interrupts.
Consistent with the PCI Spec, the PLB master is required to perform the write again if the last of the
automatic retries was terminated with a PCI retry.
• If on a single transfer or on a burst transfer a PERR error during data phase is detected, the PLB PCI
Bridge aborts the PCI transaction and a PLB Master Write PERR interrupt is asserted. If the burst
transfer is still in progress, an
Sl_MErr is asserted with Sl_wrDAck . The IPIF2PCI FIFO is flushed
upon asserting the PERR Write interrupt. The Detected Parity Error status register bit is set as well.
• If on a burst transfer, the initiator latency timer expires, the PLB PCI Bridge terminates the PCI