Xilinx LogiCore PLB PCI Full Bridge - Manual (Page 22)

PLB PCI Full Bridge (v1.00a)
22 www.xilinx.com DS508 March 21, 2006
Product Specification
EARL
Y ACCESS
Supported PCI Bus Commands
The list of commands supported by the LogiCORE PCI interface is provided in Table 4 .
G62 C_NUM_IDSEL
G49 and
G63
G61 and
G63
If G61=0, G62 has no meaning. If
G61=1, G62 sets the number of devices
supported in configuration operations.
Must be sufficiently large to include the
address bit defined by G63. If G49=1,
G62 restricts the allowed values that are
meaningful in the Device Number
Register
G63
C_BRIDGE_IDSEL_ADDR
_BIT
G62
G49, G61
and G62
If G61=0 or G49=1, G63 has no
meaning. If G61=1 and G49=0, G63
must be consistent with the setting of
G62
IPIF Parameters Group
G64 C_PLB_MID_WIDTH
G65 C_PLB_NUM_MASTERS
G66 C_PLB_AWIDTH
G67 C_PLB_DWIDTH
G68 C_FAMILY G50-52
If G68
≠ Virtex-4, G50-52 have no
meanings.
Table 4: Supported PCI Bus Commands
Command PLB PCI Bridge
Code Name Target Initiator
0000 Interrupt Acknowledge No No
0001 Special Cycle No No
0010 I/O Read No Yes
0011 I/O Write No Yes
0100 Reserved Ignore Ignore
0101 Reserved Ignore Ignore
0110 Memory Read Yes Yes
0111 Memory Write Yes Yes
1000 Reserved Ignore Ignore
1001 Reserved Ignore Ignore
1010 Configuration Read Yes Optional
1011 Configuration Write Yes Optional
1100 Memory Read Multiple Yes Yes
Table 3: PLB PCI Bridge Parameters-Port Dependencies (Contd)
Generic Parameter Affects Depends Description