Teledyne LeCroy QPHY-HDMI - Manual (Page 20)

QPHY-HDMI Test Descriptions
These are the standard HDMI compliance tests.
Test7-2: TMDS-VL
This test confirms that DC voltage levels on the HDMI link are within specified limits for each
TMDS signal.
R EQUIREMENT
Single-ended, low level output voltage, VL:
If attached Sink supports only <=165MHz : (AVcc -
600mVolts) ≤ VL ≤ (AVcc - 400mVolts)
If attached Sink supports >165MHz : (AVcc -
700mVolts) ≤ VL ≤ (AVcc - 400mVolts)
Reference: [HDMI: Table 4-15] Source DC Characteristics at TP1
M ETHODOLOGY
1. Connect TPA-P adapter to Source DUT HDMI output connector.
2. Connect TF-HDMI-3.3V to TMDS_DATA0+.
3. Configure the EDID to indicate only 27MHz formats (480p and 576p, no Deep Color
support) with the 640x480p Established Timings bit set.
4. Control the Source DUT to output a video format with lowest supported TMDS clock
frequency (typically 27MHz).
5. Capture 1000 or more repetitions, triggered at the vertical mid-point of the High-to-Low
transition of a H-L-L-L bit sequence. Each capture must be of duration 3*TBIT.
6. Display the voltage (vertical) histogram on the scope, with the histogram data
accumulated only from the last 2-bits of the H-L-L-L sequence.
7. Read the VL value as the most common low-level voltage shown on the histogram. If (VL
> 2.90V) OR (VL < 2.70V) then
8. Capture 10,000 repetitions, triggered at mid-
point of waveform, of duration ≥ 2*TBIT to
get proper histograms.
9. Display the voltage (vertical) histogram on the scope. If (VL > 2.90V) OR (VL < 2.70V)
then FAIL
10. Repeat the test for all eight TMDS signals.
11. If CDF field Source_Above_165 , then switch to an EDID that additionally indicates:
a. Support for 1080p50Hz and 60Hz
b. Deep Color 36-bits/pixel
c. Max_TMDS_Clock of 225MHz (value = 225/5 = 45)
12. Repeat test sequence above still using lowest clock rate format. If (VL > 2.90V) OR (VL
< 2.60V) then FAIL.
13. Repeat the test for all eight TMDS signals.
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